Amiccom Electronics Co., Ltd. A8137M 2025.07.01 A8137M0 SVD File CM0 r0p0 little 2 false 8 32 DUALTIMER1 Dual Timer DUALTIMER 0x40002000 0x0 0x20 registers n DUALTIMER 10 DUALTMR1_BGLOAD Dual Timer 1 Back Ground Load register 0x18 32 read-write n 0x0 0xFFFFFFFF DUALTMR1_CTRL Dual Timer 1 Control register 0x8 32 read-write n 0x0 0xF EN Dual timer x Enable 7 8 read-write 0 Disable 0 1 Enable (Dual timer start count down) 1 INTEN Dual timer interrupt enable 5 6 read-write 0 Dual Timer interrupt disable 0 1 Dual Timer interrupt enable 1 MD Dual timer Mode 6 7 read-write 0 Free-running mode 0 1 Periodic mode 1 OS Dual timer one-shot count selects 0 1 read-write 0 Wrapping 0 1 One-shot 1 PRE Dual timer size selects 16-bit or 32-bit counter operation 2 4 read-write Dual timer prescale Undefined 3 Dual timer prescale Undefined 3 Dual timer prescale Undefined 3 Dual timer prescale Undefined 3 SLT Dual timer size selects 16-bit or 32-bit counter operation 1 2 read-write 0 16-bit counter 0 1 32-bit counter 1 DUALTMR1_INTCLR Dual Timer 1 Interrupt Clear register 0xC 32 write-only n 0x0 0x1 INTCLR Timer interrupt clear. Write any value to this register to clean RIS and MIS. 0 1 write-only 0 Timer interrupt clear 0 1 Timer interrupt clear 1 DUALTMR1_LOAD Dual Timer 1 Load register 0x0 32 read-write n 0x0 0xFFFFFFFF DUALTMR1_MIS Dual Timer 1 Mask Interrupt register 0x14 32 read-only n 0x0 0x1 MIS Dual timer interrupt enabled status from the counter 0 1 read-only 0 INTEN=0 or RIS=0. Dual Timer interrupt not occur 0 1 INTEN=1 and RIS=1. Dual Timer interrupt occur 1 DUALTMR1_RIS Dual Timer 1 Raw Interrupt register 0x10 32 read-only n 0x0 0x1 RIS Dual timer Raw interrupt status 0 1 read-only 0 VALUE[31:0] not counts down to 0 0 1 VALUE[31:0] had counted down to 0 1 DUALTMR1_VALUE Dual Timer 1 current Value register 0x4 32 read-write n 0x0 0xFFFFFFFF DUALTIMER2 Dual Timer DUALTIMER 0x40002020 0x0 0x20 registers n DUALTIMER 10 DUALTMR2_BGLOAD Dual Timer 2 Back Ground Load register 0x18 32 read-write n 0x0 0xFFFFFFFF DUALTMR2_CTRL Dual Timer 2 Control register 0x8 32 read-write n 0x0 0xF EN Dual timer x Enable 7 8 read-write 0 Disable 0 1 Enable (Dual timer start count down) 1 INTEN Dual timer interrupt enable 5 6 read-write 0 Dual Timer interrupt disable 0 1 Dual Timer interrupt enable 1 MD Dual timer Mode 6 7 read-write 0 Free-running mode 0 1 Periodic mode 1 OS Dual timer one-shot count selects 0 1 read-write 0 Wrapping 0 1 One-shot 1 PRE Dual timer size selects 16-bit or 32-bit counter operation 2 4 read-write Dual timer prescale Undefined 3 Dual timer prescale Undefined 3 Dual timer prescale Undefined 3 Dual timer prescale Undefined 3 SLT Dual timer size selects 16-bit or 32-bit counter operation 1 2 read-write 0 16-bit counter 0 1 32-bit counter 1 DUALTMR2_INTCLR Dual Timer 2 Interrupt Clear register 0xC 32 write-only n 0x0 0x1 INTCLR Timer interrupt clear. Write any value to this register to clean RIS and MIS. 0 1 write-only 0 Timer interrupt clear 0 1 Timer interrupt clear 1 DUALTMR2_LOAD Dual Timer 2 Load register 0x0 32 read-write n 0x0 0xFFFFFFFF DUALTMR2_MIS Dual Timer 2 Mask Interrupt register 0x14 32 read-only n 0x0 0x1 MIS Dual timer interrupt enabled status from the counter 0 1 read-only 0 INTEN=0 or RIS=0. Dual Timer interrupt not occur 0 1 INTEN=1 and RIS=1. Dual Timer interrupt occur 1 DUALTMR2_RIS Dual Timer 2 Raw Interrupt register 0x10 32 read-only n 0x0 0x1 RIS Dual timer Raw interrupt status 0 1 read-only 0 VALUE[31:0] not counts down to 0 0 1 VALUE[31:0] had counted down to 0 1 DUALTMR2_VALUE Dual Timer 2 current Value register 0x4 32 read-write n 0x0 0xFFFFFFFF GPIO0 General Purpose I/O GPIO 0x40010000 0x0 0x1000 registers n GPIO0 6 LB_MASKED0 Lower byte Masked Access Register 0x400 32 read-write n 0x0 0xFFFFFFFF LB_MASKED1 Lower byte Masked Access Register 0x404 32 read-write n 0x0 0xFFFFFFFF LB_MASKED10 Lower byte Masked Access Register 0x428 32 read-write n 0x0 0xFFFFFFFF LB_MASKED100 Lower byte Masked Access Register 0x590 32 read-write n 0x0 0xFFFFFFFF LB_MASKED101 Lower byte Masked Access Register 0x594 32 read-write n 0x0 0xFFFFFFFF LB_MASKED102 Lower byte Masked Access Register 0x598 32 read-write n 0x0 0xFFFFFFFF LB_MASKED103 Lower byte Masked Access Register 0x59C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED104 Lower byte Masked Access Register 0x5A0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED105 Lower byte Masked Access Register 0x5A4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED106 Lower byte Masked Access Register 0x5A8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED107 Lower byte Masked Access Register 0x5AC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED108 Lower byte Masked Access Register 0x5B0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED109 Lower byte Masked Access Register 0x5B4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED11 Lower byte Masked Access Register 0x42C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED110 Lower byte Masked Access Register 0x5B8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED111 Lower byte Masked Access Register 0x5BC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED112 Lower byte Masked Access Register 0x5C0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED113 Lower byte Masked Access Register 0x5C4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED114 Lower byte Masked Access Register 0x5C8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED115 Lower byte Masked Access Register 0x5CC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED116 Lower byte Masked Access Register 0x5D0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED117 Lower byte Masked Access Register 0x5D4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED118 Lower byte Masked Access Register 0x5D8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED119 Lower byte Masked Access Register 0x5DC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED12 Lower byte Masked Access Register 0x430 32 read-write n 0x0 0xFFFFFFFF LB_MASKED120 Lower byte Masked Access Register 0x5E0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED121 Lower byte Masked Access Register 0x5E4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED122 Lower byte Masked Access Register 0x5E8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED123 Lower byte Masked Access Register 0x5EC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED124 Lower byte Masked Access Register 0x5F0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED125 Lower byte Masked Access Register 0x5F4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED126 Lower byte Masked Access Register 0x5F8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED127 Lower byte Masked Access Register 0x5FC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED128 Lower byte Masked Access Register 0x600 32 read-write n 0x0 0xFFFFFFFF LB_MASKED129 Lower byte Masked Access Register 0x604 32 read-write n 0x0 0xFFFFFFFF LB_MASKED13 Lower byte Masked Access Register 0x434 32 read-write n 0x0 0xFFFFFFFF LB_MASKED130 Lower byte Masked Access Register 0x608 32 read-write n 0x0 0xFFFFFFFF LB_MASKED131 Lower byte Masked Access Register 0x60C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED132 Lower byte Masked Access Register 0x610 32 read-write n 0x0 0xFFFFFFFF LB_MASKED133 Lower byte Masked Access Register 0x614 32 read-write n 0x0 0xFFFFFFFF LB_MASKED134 Lower byte Masked Access Register 0x618 32 read-write n 0x0 0xFFFFFFFF LB_MASKED135 Lower byte Masked Access Register 0x61C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED136 Lower byte Masked Access Register 0x620 32 read-write n 0x0 0xFFFFFFFF LB_MASKED137 Lower byte Masked Access Register 0x624 32 read-write n 0x0 0xFFFFFFFF LB_MASKED138 Lower byte Masked Access Register 0x628 32 read-write n 0x0 0xFFFFFFFF LB_MASKED139 Lower byte Masked Access Register 0x62C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED14 Lower byte Masked Access Register 0x438 32 read-write n 0x0 0xFFFFFFFF LB_MASKED140 Lower byte Masked Access Register 0x630 32 read-write n 0x0 0xFFFFFFFF LB_MASKED141 Lower byte Masked Access Register 0x634 32 read-write n 0x0 0xFFFFFFFF LB_MASKED142 Lower byte Masked Access Register 0x638 32 read-write n 0x0 0xFFFFFFFF LB_MASKED143 Lower byte Masked Access Register 0x63C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED144 Lower byte Masked Access Register 0x640 32 read-write n 0x0 0xFFFFFFFF LB_MASKED145 Lower byte Masked Access Register 0x644 32 read-write n 0x0 0xFFFFFFFF LB_MASKED146 Lower byte Masked Access Register 0x648 32 read-write n 0x0 0xFFFFFFFF LB_MASKED147 Lower byte Masked Access Register 0x64C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED148 Lower byte Masked Access Register 0x650 32 read-write n 0x0 0xFFFFFFFF LB_MASKED149 Lower byte Masked Access Register 0x654 32 read-write n 0x0 0xFFFFFFFF LB_MASKED15 Lower byte Masked Access Register 0x43C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED150 Lower byte Masked Access Register 0x658 32 read-write n 0x0 0xFFFFFFFF LB_MASKED151 Lower byte Masked Access Register 0x65C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED152 Lower byte Masked Access Register 0x660 32 read-write n 0x0 0xFFFFFFFF LB_MASKED153 Lower byte Masked Access Register 0x664 32 read-write n 0x0 0xFFFFFFFF LB_MASKED154 Lower byte Masked Access Register 0x668 32 read-write n 0x0 0xFFFFFFFF LB_MASKED155 Lower byte Masked Access Register 0x66C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED156 Lower byte Masked Access Register 0x670 32 read-write n 0x0 0xFFFFFFFF LB_MASKED157 Lower byte Masked Access Register 0x674 32 read-write n 0x0 0xFFFFFFFF LB_MASKED158 Lower byte Masked Access Register 0x678 32 read-write n 0x0 0xFFFFFFFF LB_MASKED159 Lower byte Masked Access Register 0x67C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED16 Lower byte Masked Access Register 0x440 32 read-write n 0x0 0xFFFFFFFF LB_MASKED160 Lower byte Masked Access Register 0x680 32 read-write n 0x0 0xFFFFFFFF LB_MASKED161 Lower byte Masked Access Register 0x684 32 read-write n 0x0 0xFFFFFFFF LB_MASKED162 Lower byte Masked Access Register 0x688 32 read-write n 0x0 0xFFFFFFFF LB_MASKED163 Lower byte Masked Access Register 0x68C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED164 Lower byte Masked Access Register 0x690 32 read-write n 0x0 0xFFFFFFFF LB_MASKED165 Lower byte Masked Access Register 0x694 32 read-write n 0x0 0xFFFFFFFF LB_MASKED166 Lower byte Masked Access Register 0x698 32 read-write n 0x0 0xFFFFFFFF LB_MASKED167 Lower byte Masked Access Register 0x69C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED168 Lower byte Masked Access Register 0x6A0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED169 Lower byte Masked Access Register 0x6A4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED17 Lower byte Masked Access Register 0x444 32 read-write n 0x0 0xFFFFFFFF LB_MASKED170 Lower byte Masked Access Register 0x6A8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED171 Lower byte Masked Access Register 0x6AC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED172 Lower byte Masked Access Register 0x6B0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED173 Lower byte Masked Access Register 0x6B4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED174 Lower byte Masked Access Register 0x6B8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED175 Lower byte Masked Access Register 0x6BC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED176 Lower byte Masked Access Register 0x6C0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED177 Lower byte Masked Access Register 0x6C4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED178 Lower byte Masked Access Register 0x6C8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED179 Lower byte Masked Access Register 0x6CC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED18 Lower byte Masked Access Register 0x448 32 read-write n 0x0 0xFFFFFFFF LB_MASKED180 Lower byte Masked Access Register 0x6D0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED181 Lower byte Masked Access Register 0x6D4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED182 Lower byte Masked Access Register 0x6D8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED183 Lower byte Masked Access Register 0x6DC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED184 Lower byte Masked Access Register 0x6E0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED185 Lower byte Masked Access Register 0x6E4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED186 Lower byte Masked Access Register 0x6E8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED187 Lower byte Masked Access Register 0x6EC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED188 Lower byte Masked Access Register 0x6F0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED189 Lower byte Masked Access Register 0x6F4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED19 Lower byte Masked Access Register 0x44C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED190 Lower byte Masked Access Register 0x6F8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED191 Lower byte Masked Access Register 0x6FC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED192 Lower byte Masked Access Register 0x700 32 read-write n 0x0 0xFFFFFFFF LB_MASKED193 Lower byte Masked Access Register 0x704 32 read-write n 0x0 0xFFFFFFFF LB_MASKED194 Lower byte Masked Access Register 0x708 32 read-write n 0x0 0xFFFFFFFF LB_MASKED195 Lower byte Masked Access Register 0x70C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED196 Lower byte Masked Access Register 0x710 32 read-write n 0x0 0xFFFFFFFF LB_MASKED197 Lower byte Masked Access Register 0x714 32 read-write n 0x0 0xFFFFFFFF LB_MASKED198 Lower byte Masked Access Register 0x718 32 read-write n 0x0 0xFFFFFFFF LB_MASKED199 Lower byte Masked Access Register 0x71C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED2 Lower byte Masked Access Register 0x408 32 read-write n 0x0 0xFFFFFFFF LB_MASKED20 Lower byte Masked Access Register 0x450 32 read-write n 0x0 0xFFFFFFFF LB_MASKED200 Lower byte Masked Access Register 0x720 32 read-write n 0x0 0xFFFFFFFF LB_MASKED201 Lower byte Masked Access Register 0x724 32 read-write n 0x0 0xFFFFFFFF LB_MASKED202 Lower byte Masked Access Register 0x728 32 read-write n 0x0 0xFFFFFFFF LB_MASKED203 Lower byte Masked Access Register 0x72C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED204 Lower byte Masked Access Register 0x730 32 read-write n 0x0 0xFFFFFFFF LB_MASKED205 Lower byte Masked Access Register 0x734 32 read-write n 0x0 0xFFFFFFFF LB_MASKED206 Lower byte Masked Access Register 0x738 32 read-write n 0x0 0xFFFFFFFF LB_MASKED207 Lower byte Masked Access Register 0x73C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED208 Lower byte Masked Access Register 0x740 32 read-write n 0x0 0xFFFFFFFF LB_MASKED209 Lower byte Masked Access Register 0x744 32 read-write n 0x0 0xFFFFFFFF LB_MASKED21 Lower byte Masked Access Register 0x454 32 read-write n 0x0 0xFFFFFFFF LB_MASKED210 Lower byte Masked Access Register 0x748 32 read-write n 0x0 0xFFFFFFFF LB_MASKED211 Lower byte Masked Access Register 0x74C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED212 Lower byte Masked Access Register 0x750 32 read-write n 0x0 0xFFFFFFFF LB_MASKED213 Lower byte Masked Access Register 0x754 32 read-write n 0x0 0xFFFFFFFF LB_MASKED214 Lower byte Masked Access Register 0x758 32 read-write n 0x0 0xFFFFFFFF LB_MASKED215 Lower byte Masked Access Register 0x75C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED216 Lower byte Masked Access Register 0x760 32 read-write n 0x0 0xFFFFFFFF LB_MASKED217 Lower byte Masked Access Register 0x764 32 read-write n 0x0 0xFFFFFFFF LB_MASKED218 Lower byte Masked Access Register 0x768 32 read-write n 0x0 0xFFFFFFFF LB_MASKED219 Lower byte Masked Access Register 0x76C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED22 Lower byte Masked Access Register 0x458 32 read-write n 0x0 0xFFFFFFFF LB_MASKED220 Lower byte Masked Access Register 0x770 32 read-write n 0x0 0xFFFFFFFF LB_MASKED221 Lower byte Masked Access Register 0x774 32 read-write n 0x0 0xFFFFFFFF LB_MASKED222 Lower byte Masked Access Register 0x778 32 read-write n 0x0 0xFFFFFFFF LB_MASKED223 Lower byte Masked Access Register 0x77C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED224 Lower byte Masked Access Register 0x780 32 read-write n 0x0 0xFFFFFFFF LB_MASKED225 Lower byte Masked Access Register 0x784 32 read-write n 0x0 0xFFFFFFFF LB_MASKED226 Lower byte Masked Access Register 0x788 32 read-write n 0x0 0xFFFFFFFF LB_MASKED227 Lower byte Masked Access Register 0x78C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED228 Lower byte Masked Access Register 0x790 32 read-write n 0x0 0xFFFFFFFF LB_MASKED229 Lower byte Masked Access Register 0x794 32 read-write n 0x0 0xFFFFFFFF LB_MASKED23 Lower byte Masked Access Register 0x45C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED230 Lower byte Masked Access Register 0x798 32 read-write n 0x0 0xFFFFFFFF LB_MASKED231 Lower byte Masked Access Register 0x79C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED232 Lower byte Masked Access Register 0x7A0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED233 Lower byte Masked Access Register 0x7A4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED234 Lower byte Masked Access Register 0x7A8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED235 Lower byte Masked Access Register 0x7AC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED236 Lower byte Masked Access Register 0x7B0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED237 Lower byte Masked Access Register 0x7B4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED238 Lower byte Masked Access Register 0x7B8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED239 Lower byte Masked Access Register 0x7BC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED24 Lower byte Masked Access Register 0x460 32 read-write n 0x0 0xFFFFFFFF LB_MASKED240 Lower byte Masked Access Register 0x7C0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED241 Lower byte Masked Access Register 0x7C4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED242 Lower byte Masked Access Register 0x7C8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED243 Lower byte Masked Access Register 0x7CC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED244 Lower byte Masked Access Register 0x7D0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED245 Lower byte Masked Access Register 0x7D4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED246 Lower byte Masked Access Register 0x7D8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED247 Lower byte Masked Access Register 0x7DC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED248 Lower byte Masked Access Register 0x7E0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED249 Lower byte Masked Access Register 0x7E4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED25 Lower byte Masked Access Register 0x464 32 read-write n 0x0 0xFFFFFFFF LB_MASKED250 Lower byte Masked Access Register 0x7E8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED251 Lower byte Masked Access Register 0x7EC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED252 Lower byte Masked Access Register 0x7F0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED253 Lower byte Masked Access Register 0x7F4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED254 Lower byte Masked Access Register 0x7F8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED255 Lower byte Masked Access Register 0x7FC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED26 Lower byte Masked Access Register 0x468 32 read-write n 0x0 0xFFFFFFFF LB_MASKED27 Lower byte Masked Access Register 0x46C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED28 Lower byte Masked Access Register 0x470 32 read-write n 0x0 0xFFFFFFFF LB_MASKED29 Lower byte Masked Access Register 0x474 32 read-write n 0x0 0xFFFFFFFF LB_MASKED3 Lower byte Masked Access Register 0x40C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED30 Lower byte Masked Access Register 0x478 32 read-write n 0x0 0xFFFFFFFF LB_MASKED31 Lower byte Masked Access Register 0x47C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED32 Lower byte Masked Access Register 0x480 32 read-write n 0x0 0xFFFFFFFF LB_MASKED33 Lower byte Masked Access Register 0x484 32 read-write n 0x0 0xFFFFFFFF LB_MASKED34 Lower byte Masked Access Register 0x488 32 read-write n 0x0 0xFFFFFFFF LB_MASKED35 Lower byte Masked Access Register 0x48C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED36 Lower byte Masked Access Register 0x490 32 read-write n 0x0 0xFFFFFFFF LB_MASKED37 Lower byte Masked Access Register 0x494 32 read-write n 0x0 0xFFFFFFFF LB_MASKED38 Lower byte Masked Access Register 0x498 32 read-write n 0x0 0xFFFFFFFF LB_MASKED39 Lower byte Masked Access Register 0x49C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED4 Lower byte Masked Access Register 0x410 32 read-write n 0x0 0xFFFFFFFF LB_MASKED40 Lower byte Masked Access Register 0x4A0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED41 Lower byte Masked Access Register 0x4A4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED42 Lower byte Masked Access Register 0x4A8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED43 Lower byte Masked Access Register 0x4AC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED44 Lower byte Masked Access Register 0x4B0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED45 Lower byte Masked Access Register 0x4B4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED46 Lower byte Masked Access Register 0x4B8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED47 Lower byte Masked Access Register 0x4BC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED48 Lower byte Masked Access Register 0x4C0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED49 Lower byte Masked Access Register 0x4C4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED5 Lower byte Masked Access Register 0x414 32 read-write n 0x0 0xFFFFFFFF LB_MASKED50 Lower byte Masked Access Register 0x4C8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED51 Lower byte Masked Access Register 0x4CC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED52 Lower byte Masked Access Register 0x4D0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED53 Lower byte Masked Access Register 0x4D4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED54 Lower byte Masked Access Register 0x4D8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED55 Lower byte Masked Access Register 0x4DC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED56 Lower byte Masked Access Register 0x4E0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED57 Lower byte Masked Access Register 0x4E4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED58 Lower byte Masked Access Register 0x4E8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED59 Lower byte Masked Access Register 0x4EC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED6 Lower byte Masked Access Register 0x418 32 read-write n 0x0 0xFFFFFFFF LB_MASKED60 Lower byte Masked Access Register 0x4F0 32 read-write n 0x0 0xFFFFFFFF LB_MASKED61 Lower byte Masked Access Register 0x4F4 32 read-write n 0x0 0xFFFFFFFF LB_MASKED62 Lower byte Masked Access Register 0x4F8 32 read-write n 0x0 0xFFFFFFFF LB_MASKED63 Lower byte Masked Access Register 0x4FC 32 read-write n 0x0 0xFFFFFFFF LB_MASKED64 Lower byte Masked Access Register 0x500 32 read-write n 0x0 0xFFFFFFFF LB_MASKED65 Lower byte Masked Access Register 0x504 32 read-write n 0x0 0xFFFFFFFF LB_MASKED66 Lower byte Masked Access Register 0x508 32 read-write n 0x0 0xFFFFFFFF LB_MASKED67 Lower byte Masked Access Register 0x50C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED68 Lower byte Masked Access Register 0x510 32 read-write n 0x0 0xFFFFFFFF LB_MASKED69 Lower byte Masked Access Register 0x514 32 read-write n 0x0 0xFFFFFFFF LB_MASKED7 Lower byte Masked Access Register 0x41C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED70 Lower byte Masked Access Register 0x518 32 read-write n 0x0 0xFFFFFFFF LB_MASKED71 Lower byte Masked Access Register 0x51C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED72 Lower byte Masked Access Register 0x520 32 read-write n 0x0 0xFFFFFFFF LB_MASKED73 Lower byte Masked Access Register 0x524 32 read-write n 0x0 0xFFFFFFFF LB_MASKED74 Lower byte Masked Access Register 0x528 32 read-write n 0x0 0xFFFFFFFF LB_MASKED75 Lower byte Masked Access Register 0x52C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED76 Lower byte Masked Access Register 0x530 32 read-write n 0x0 0xFFFFFFFF LB_MASKED77 Lower byte Masked Access Register 0x534 32 read-write n 0x0 0xFFFFFFFF LB_MASKED78 Lower byte Masked Access Register 0x538 32 read-write n 0x0 0xFFFFFFFF LB_MASKED79 Lower byte Masked Access Register 0x53C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED8 Lower byte Masked Access Register 0x420 32 read-write n 0x0 0xFFFFFFFF LB_MASKED80 Lower byte Masked Access Register 0x540 32 read-write n 0x0 0xFFFFFFFF LB_MASKED81 Lower byte Masked Access Register 0x544 32 read-write n 0x0 0xFFFFFFFF LB_MASKED82 Lower byte Masked Access Register 0x548 32 read-write n 0x0 0xFFFFFFFF LB_MASKED83 Lower byte Masked Access Register 0x54C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED84 Lower byte Masked Access Register 0x550 32 read-write n 0x0 0xFFFFFFFF LB_MASKED85 Lower byte Masked Access Register 0x554 32 read-write n 0x0 0xFFFFFFFF LB_MASKED86 Lower byte Masked Access Register 0x558 32 read-write n 0x0 0xFFFFFFFF LB_MASKED87 Lower byte Masked Access Register 0x55C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED88 Lower byte Masked Access Register 0x560 32 read-write n 0x0 0xFFFFFFFF LB_MASKED89 Lower byte Masked Access Register 0x564 32 read-write n 0x0 0xFFFFFFFF LB_MASKED9 Lower byte Masked Access Register 0x424 32 read-write n 0x0 0xFFFFFFFF LB_MASKED90 Lower byte Masked Access Register 0x568 32 read-write n 0x0 0xFFFFFFFF LB_MASKED91 Lower byte Masked Access Register 0x56C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED92 Lower byte Masked Access Register 0x570 32 read-write n 0x0 0xFFFFFFFF LB_MASKED93 Lower byte Masked Access Register 0x574 32 read-write n 0x0 0xFFFFFFFF LB_MASKED94 Lower byte Masked Access Register 0x578 32 read-write n 0x0 0xFFFFFFFF LB_MASKED95 Lower byte Masked Access Register 0x57C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED96 Lower byte Masked Access Register 0x580 32 read-write n 0x0 0xFFFFFFFF LB_MASKED97 Lower byte Masked Access Register 0x584 32 read-write n 0x0 0xFFFFFFFF LB_MASKED98 Lower byte Masked Access Register 0x588 32 read-write n 0x0 0xFFFFFFFF LB_MASKED99 Lower byte Masked Access Register 0x58C 32 read-write n 0x0 0xFFFFFFFF LB_MASKED[%s] Lower byte Masked Access Register 0x800 32 read-write n 0x0 0xFFFFFFFF P0ALTFUNCCLR Port 0 Alternative Function Clear Register 0x1C 32 read-write n 0x0 0xFFFFFF P0ALTFUNCCLR0 Alternative Function Clear of GPIO0.0 0 1 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.0 1 P0ALTFUNCCLR1 Alternative Function Clear of GPIO0.1 1 2 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.1 1 P0ALTFUNCCLR10 Alternative Function Clear of GPIO0.10 10 11 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.10 1 P0ALTFUNCCLR11 Alternative Function Clear of GPIO0.11 11 12 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.11 1 P0ALTFUNCCLR12 Alternative Function Clear of GPIO0.12 12 13 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.12 1 P0ALTFUNCCLR13 Alternative Function Clear of GPIO0.13 13 14 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.13 1 P0ALTFUNCCLR14 Alternative Function Clear of GPIO0.14 14 15 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.14 1 P0ALTFUNCCLR15 Alternative Function Clear of GPIO0.15 15 16 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.15 1 P0ALTFUNCCLR16 Alternative Function Clear of GPIO0.16 16 17 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.16 1 P0ALTFUNCCLR17 Alternative Function Clear of GPIO0.17 17 18 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.17 1 P0ALTFUNCCLR18 Alternative Function Clear of GPIO0.18 18 19 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.18 1 P0ALTFUNCCLR19 Alternative Function Clear of GPIO0.19 19 20 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.19 1 P0ALTFUNCCLR2 Alternative Function Clear of GPIO0.2 2 3 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.2 1 P0ALTFUNCCLR20 Alternative Function Clear of GPIO0.20 20 21 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.20 1 P0ALTFUNCCLR21 Alternative Function Clear of GPIO0.21 21 22 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.21 1 P0ALTFUNCCLR22 Alternative Function Clear of GPIO0.22 22 23 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.22 1 P0ALTFUNCCLR23 Alternative Function Clear of GPIO0.23 23 24 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.23 1 P0ALTFUNCCLR3 Alternative Function Clear of GPIO0.3 3 4 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.3 1 P0ALTFUNCCLR4 Alternative Function Clear of GPIO0.4 4 5 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.4 1 P0ALTFUNCCLR5 Alternative Function Clear of GPIO0.5 5 6 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.5 1 P0ALTFUNCCLR6 Alternative Function Clear of GPIO0.6 6 7 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.6 1 P0ALTFUNCCLR7 Alternative Function Clear of GPIO0.7 7 8 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.7 1 P0ALTFUNCCLR8 Alternative Function Clear of GPIO0.8 8 9 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.8 1 P0ALTFUNCCLR9 Alternative Function Clear of GPIO0.9 9 10 read-write 0 No effect 0 1 Alternative Function Clear of GPIO0.9 1 P0ALTFUNCSET Port 0 Alternative Function Set Register 0x18 32 read-write n 0x0 0xFFFFFF P0ALTFUNCSET0 Alternative Function Set of GPIO0.0 0 1 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.0 1 P0ALTFUNCSET1 Alternative Function Set of GPIO0.1 1 2 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.1 1 P0ALTFUNCSET10 Alternative Function Set of GPIO0.10 10 11 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.10 1 P0ALTFUNCSET11 Alternative Function Set of GPIO0.11 11 12 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.11 1 P0ALTFUNCSET12 Alternative Function Set of GPIO0.12 12 13 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.12 1 P0ALTFUNCSET13 Alternative Function Set of GPIO0.13 13 14 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.13 1 P0ALTFUNCSET14 Alternative Function Set of GPIO0.14 14 15 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.14 1 P0ALTFUNCSET15 Alternative Function Set of GPIO0.15 15 16 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.15 1 P0ALTFUNCSET16 Alternative Function Set of GPIO0.16 16 17 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.16 1 P0ALTFUNCSET17 Alternative Function Set of GPIO0.17 17 18 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.17 1 P0ALTFUNCSET18 Alternative Function Set of GPIO0.18 18 19 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.18 1 P0ALTFUNCSET19 Alternative Function Set of GPIO0.19 19 20 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.19 1 P0ALTFUNCSET2 Alternative Function Set of GPIO0.2 2 3 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.2 1 P0ALTFUNCSET20 Alternative Function Set of GPIO0.20 20 21 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.20 1 P0ALTFUNCSET21 Alternative Function Set of GPIO0.21 21 22 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.21 1 P0ALTFUNCSET22 Alternative Function Set of GPIO0.22 22 23 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.22 1 P0ALTFUNCSET23 Alternative Function Set of GPIO0.23 23 24 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.23 1 P0ALTFUNCSET3 Alternative Function Set of GPIO0.3 3 4 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.3 1 P0ALTFUNCSET4 Alternative Function Set of GPIO0.4 4 5 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.4 1 P0ALTFUNCSET5 Alternative Function Set of GPIO0.5 5 6 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.5 1 P0ALTFUNCSET6 Alternative Function Set of GPIO0.6 6 7 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.6 1 P0ALTFUNCSET7 Alternative Function Set of GPIO0.7 7 8 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.7 1 P0ALTFUNCSET8 Alternative Function Set of GPIO0.8 8 9 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.8 1 P0ALTFUNCSET9 Alternative Function Set of GPIO0.9 9 10 read-write 0 No effect 0 1 Alternative Function Set of GPIO0.9 1 P0DATA Port 0 Data Register 0x0 32 read-write n 0x0 0xFFFFFF P0DATA0 Data of GPIO0.0 0 1 read-write 0 GPIO0.0 is 0 0 1 GPIO0.0 is 1 1 P0DATA1 Data of GPIO0.1 1 2 read-write 0 GPIO0.1 is 0 0 1 GPIO0.1 is 1 1 P0DATA10 Data of GPIO0.10 10 11 read-write 0 GPIO0.10 is 0 0 1 GPIO0.10 is 1 1 P0DATA11 Data of GPIO0.11 11 12 read-write 0 GPIO0.11 is 0 0 1 GPIO0.11 is 1 1 P0DATA12 Data of GPIO0.12 12 13 read-write 0 GPIO0.12 is 0 0 1 GPIO0.12 is 1 1 P0DATA13 Data of GPIO0.13 13 14 read-write 0 GPIO0.13 is 0 0 1 GPIO0.13 is 1 1 P0DATA14 Data of GPIO0.14 14 15 read-write 0 GPIO0.14 is 0 0 1 GPIO0.14 is 1 1 P0DATA15 Data of GPIO0.15 15 16 read-write 0 GPIO0.15 is 0 0 1 GPIO0.15 is 1 1 P0DATA16 Data of GPIO0.16 16 17 read-write 0 GPIO0.16 is 0 0 1 GPIO0.16 is 1 1 P0DATA17 Data of GPIO0.17 17 18 read-write 0 GPIO0.17 is 0 0 1 GPIO0.17 is 1 1 P0DATA18 Data of GPIO0.18 18 19 read-write 0 GPIO0.18 is 0 0 1 GPIO0.18 is 1 1 P0DATA19 Data of GPIO0.19 19 20 read-write 0 GPIO0.19 is 0 0 1 GPIO0.19 is 1 1 P0DATA2 Data of GPIO0.2 2 3 read-write 0 GPIO0.2 is 0 0 1 GPIO0.2 is 1 1 P0DATA20 Data of GPIO0.20 20 21 read-write 0 GPIO0.20 is 0 0 1 GPIO0.20 is 1 1 P0DATA21 Data of GPIO0.21 21 22 read-write 0 GPIO0.21 is 0 0 1 GPIO0.21 is 1 1 P0DATA22 Data of GPIO0.22 22 23 read-write 0 GPIO0.22 is 0 0 1 GPIO0.22 is 1 1 P0DATA23 Data of GPIO0.23 23 24 read-write 0 GPIO0.23 is 0 0 1 GPIO0.23 is 1 1 P0DATA3 Data of GPIO0.3 3 4 read-write 0 GPIO0.3 is 0 0 1 GPIO0.3 is 1 1 P0DATA4 Data of GPIO0.4 4 5 read-write 0 GPIO0.4 is 0 0 1 GPIO0.4 is 1 1 P0DATA5 Data of GPIO0.5 5 6 read-write 0 GPIO0.5 is 0 0 1 GPIO0.5 is 1 1 P0DATA6 Data of GPIO0.6 6 7 read-write 0 GPIO0.6 is 0 0 1 GPIO0.6 is 1 1 P0DATA7 Data of GPIO0.7 7 8 read-write 0 GPIO0.7 is 0 0 1 GPIO0.7 is 1 1 P0DATA8 Data of GPIO0.8 8 9 read-write 0 GPIO0.8 is 0 0 1 GPIO0.8 is 1 1 P0DATA9 Data of GPIO0.9 9 10 read-write 0 GPIO0.9 is 0 0 1 GPIO0.9 is 1 1 P0DATAOUT Port 0 Data Out Register 0x4 32 read-write n 0x0 0xFFFFFF P0DATAOUT0 Data Out of GPIO0.0 0 1 read-write 0 GPIO0.0 is 0 0 1 GPIO0.0 is 1 1 P0DATAOUT1 Data Out of GPIO0.1 1 2 read-write 0 GPIO0.1 is 0 0 1 GPIO0.1 is 1 1 P0DATAOUT10 Data Out of GPIO0.10 10 11 read-write 0 GPIO0.10 is 0 0 1 GPIO0.10 is 1 1 P0DATAOUT11 Data Out of GPIO0.11 11 12 read-write 0 GPIO0.11 is 0 0 1 GPIO0.11 is 1 1 P0DATAOUT12 Data Out of GPIO0.12 12 13 read-write 0 GPIO0.12 is 0 0 1 GPIO0.12 is 1 1 P0DATAOUT13 Data Out of GPIO0.13 13 14 read-write 0 GPIO0.13 is 0 0 1 GPIO0.13 is 1 1 P0DATAOUT14 Data Out of GPIO0.14 14 15 read-write 0 GPIO0.14 is 0 0 1 GPIO0.14 is 1 1 P0DATAOUT15 Data Out of GPIO0.15 15 16 read-write 0 GPIO0.15 is 0 0 1 GPIO0.15 is 1 1 P0DATAOUT16 Data Out of GPIO0.16 16 17 read-write 0 GPIO0.16 is 0 0 1 GPIO0.16 is 1 1 P0DATAOUT17 Data Out of GPIO0.17 17 18 read-write 0 GPIO0.17 is 0 0 1 GPIO0.17 is 1 1 P0DATAOUT18 Data Out of GPIO0.18 18 19 read-write 0 GPIO0.18 is 0 0 1 GPIO0.18 is 1 1 P0DATAOUT19 Data Out of GPIO0.19 19 20 read-write 0 GPIO0.19 is 0 0 1 GPIO0.19 is 1 1 P0DATAOUT2 Data Out of GPIO0.2 2 3 read-write 0 GPIO0.2 is 0 0 1 GPIO0.2 is 1 1 P0DATAOUT20 Data Out of GPIO0.20 20 21 read-write 0 GPIO0.20 is 0 0 1 GPIO0.20 is 1 1 P0DATAOUT21 Data Out of GPIO0.21 21 22 read-write 0 GPIO0.21 is 0 0 1 GPIO0.21 is 1 1 P0DATAOUT22 Data Out of GPIO0.22 22 23 read-write 0 GPIO0.22 is 0 0 1 GPIO0.22 is 1 1 P0DATAOUT23 Data Out of GPIO0.23 23 24 read-write 0 GPIO0.23 is 0 0 1 GPIO0.23 is 1 1 P0DATAOUT3 Data Out of GPIO0.3 3 4 read-write 0 GPIO0.3 is 0 0 1 GPIO0.3 is 1 1 P0DATAOUT4 Data Out of GPIO0.4 4 5 read-write 0 GPIO0.4 is 0 0 1 GPIO0.4 is 1 1 P0DATAOUT5 Data Out of GPIO0.5 5 6 read-write 0 GPIO0.5 is 0 0 1 GPIO0.5 is 1 1 P0DATAOUT6 Data Out of GPIO0.6 6 7 read-write 0 GPIO0.6 is 0 0 1 GPIO0.6 is 1 1 P0DATAOUT7 Data Out of GPIO0.7 7 8 read-write 0 GPIO0.7 is 0 0 1 GPIO0.7 is 1 1 P0DATAOUT8 Data Out of GPIO0.8 8 9 read-write 0 GPIO0.8 is 0 0 1 GPIO0.8 is 1 1 P0DATAOUT9 Data Out of GPIO0.9 9 10 read-write 0 GPIO0.9 is 0 0 1 GPIO0.9 is 1 1 P0DATAOUT_PIN Port 0 Data Out Register access by Pin P0DATAOUT 0x4 32 read-write n 0x0 0xFFFFFF P0DATA_PIN Port 0 Data Register access by Pin P0DATA 0x0 32 read-write n 0x0 0xFFFFFF P0INTCLEAR Port 0 Interrupt Request Clear Register P0INTSTATUS 0x38 32 write-only n 0x0 0xFFFFFF P0INTENCLR Port 0 Interrupt Enable Clear Register 0x24 32 read-write n 0x0 0xFFFFFF P0INTENCLR0 Interrupt Enable Clear of GPIO0.0 0 1 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.0 1 P0INTENCLR1 Interrupt Enable Clear of GPIO0.1 1 2 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.1 1 P0INTENCLR10 Interrupt Enable Clear of GPIO0.10 10 11 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.10 1 P0INTENCLR11 Interrupt Enable Clear of GPIO0.11 11 12 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.11 1 P0INTENCLR12 Interrupt Enable Clear of GPIO0.12 12 13 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.12 1 P0INTENCLR13 Interrupt Enable Clear of GPIO0.13 13 14 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.13 1 P0INTENCLR14 Interrupt Enable Clear of GPIO0.14 14 15 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.14 1 P0INTENCLR15 Interrupt Enable Clear of GPIO0.15 15 16 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.15 1 P0INTENCLR16 Interrupt Enable Clear of GPIO0.16 16 17 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.16 1 P0INTENCLR17 Interrupt Enable Clear of GPIO0.17 17 18 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.17 1 P0INTENCLR18 Interrupt Enable Clear of GPIO0.18 18 19 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.18 1 P0INTENCLR19 Interrupt Enable Clear of GPIO0.19 19 20 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.19 1 P0INTENCLR2 Interrupt Enable Clear of GPIO0.2 2 3 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.2 1 P0INTENCLR20 Interrupt Enable Clear of GPIO0.20 20 21 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.20 1 P0INTENCLR21 Interrupt Enable Clear of GPIO0.21 21 22 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.21 1 P0INTENCLR22 Interrupt Enable Clear of GPIO0.22 22 23 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.22 1 P0INTENCLR23 Interrupt Enable Clear of GPIO0.23 23 24 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.23 1 P0INTENCLR3 Interrupt Enable Clear of GPIO0.3 3 4 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.3 1 P0INTENCLR4 Interrupt Enable Clear of GPIO0.4 4 5 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.4 1 P0INTENCLR5 Interrupt Enable Clear of GPIO0.5 5 6 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.5 1 P0INTENCLR6 Interrupt Enable Clear of GPIO0.6 6 7 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.6 1 P0INTENCLR7 Interrupt Enable Clear of GPIO0.7 7 8 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.7 1 P0INTENCLR8 Interrupt Enable Clear of GPIO0.8 8 9 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.8 1 P0INTENCLR9 Interrupt Enable Clear of GPIO0.9 9 10 read-write 0 No effect 0 1 Interrupt Enable Clear of GPIO0.9 1 P0INTENSET Port 0 Interrupt Enable Set Register 0x20 32 read-write n 0x0 0xFFFFFF P0INTENSET0 Interrupt Enable Set of GPIO0.0 0 1 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.0 1 P0INTENSET1 Interrupt Enable Set of GPIO0.1 1 2 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.1 1 P0INTENSET10 Interrupt Enable Set of GPIO0.10 10 11 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.10 1 P0INTENSET11 Interrupt Enable Set of GPIO0.11 11 12 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.11 1 P0INTENSET12 Interrupt Enable Set of GPIO0.12 12 13 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.12 1 P0INTENSET13 Interrupt Enable Set of GPIO0.13 13 14 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.13 1 P0INTENSET14 Interrupt Enable Set of GPIO0.14 14 15 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.14 1 P0INTENSET15 Interrupt Enable Set of GPIO0.15 15 16 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.15 1 P0INTENSET16 Interrupt Enable Set of GPIO0.16 16 17 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.16 1 P0INTENSET17 Interrupt Enable Set of GPIO0.17 17 18 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.17 1 P0INTENSET18 Interrupt Enable Set of GPIO0.18 18 19 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.18 1 P0INTENSET19 Interrupt Enable Set of GPIO0.19 19 20 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.19 1 P0INTENSET2 Interrupt Enable Set of GPIO0.2 2 3 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.2 1 P0INTENSET20 Interrupt Enable Set of GPIO0.20 20 21 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.20 1 P0INTENSET21 Interrupt Enable Set of GPIO0.21 21 22 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.21 1 P0INTENSET22 Interrupt Enable Set of GPIO0.22 22 23 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.22 1 P0INTENSET23 Interrupt Enable Set of GPIO0.23 23 24 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.23 1 P0INTENSET3 Interrupt Enable Set of GPIO0.3 3 4 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.3 1 P0INTENSET4 Interrupt Enable Set of GPIO0.4 4 5 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.4 1 P0INTENSET5 Interrupt Enable Set of GPIO0.5 5 6 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.5 1 P0INTENSET6 Interrupt Enable Set of GPIO0.6 6 7 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.6 1 P0INTENSET7 Interrupt Enable Set of GPIO0.7 7 8 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.7 1 P0INTENSET8 Interrupt Enable Set of GPIO0.8 8 9 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.8 1 P0INTENSET9 Interrupt Enable Set of GPIO0.9 9 10 read-write 0 No effect 0 1 Interrupt Enable Set of GPIO0.9 1 P0INTPOLCLR Port 0 Interrupt Polarity Clear Register 0x34 32 read-write n 0x0 0xFFFFFF P0INTPOLCLR0 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.0 0 1 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.0 1 P0INTPOLCLR1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.1 1 2 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.1 1 P0INTPOLCLR10 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.10 10 11 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.10 1 P0INTPOLCLR11 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.11 11 12 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.11 1 P0INTPOLCLR12 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.12 12 13 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.12 1 P0INTPOLCLR13 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.13 13 14 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.13 1 P0INTPOLCLR14 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.14 14 15 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.14 1 P0INTPOLCLR15 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.15 15 16 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.15 1 P0INTPOLCLR16 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.16 16 17 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.16 1 P0INTPOLCLR17 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.17 17 18 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.17 1 P0INTPOLCLR18 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.18 18 19 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.18 1 P0INTPOLCLR19 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.19 19 20 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.19 1 P0INTPOLCLR2 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.2 2 3 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.2 1 P0INTPOLCLR20 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.20 20 21 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.20 1 P0INTPOLCLR21 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.21 21 22 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.21 1 P0INTPOLCLR22 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.22 22 23 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.22 1 P0INTPOLCLR23 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.23 23 24 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.23 1 P0INTPOLCLR3 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.3 3 4 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.3 1 P0INTPOLCLR4 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.4 4 5 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.4 1 P0INTPOLCLR5 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.5 5 6 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.5 1 P0INTPOLCLR6 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.6 6 7 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.6 1 P0INTPOLCLR7 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.7 7 8 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.7 1 P0INTPOLCLR8 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.8 8 9 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.8 1 P0INTPOLCLR9 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.9 9 10 read-write 0 No effect 0 1 Interrupt Polarity-level clean (low level or falling edge) of GPIO0.9 1 P0INTPOLSET Port 0 Interrupt Polarity Set Register 0x30 32 read-write n 0x0 0xFFFFFF P0INTPOLSET0 Interrupt Polarity-level set (high level or rising edge) of GPIO0.0 0 1 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.0 1 P0INTPOLSET1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.1 1 2 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.1 1 P0INTPOLSET10 Interrupt Polarity-level set (high level or rising edge) of GPIO0.10 10 11 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.10 1 P0INTPOLSET11 Interrupt Polarity-level set (high level or rising edge) of GPIO0.11 11 12 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.11 1 P0INTPOLSET12 Interrupt Polarity-level set (high level or rising edge) of GPIO0.12 12 13 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.12 1 P0INTPOLSET13 Interrupt Polarity-level set (high level or rising edge) of GPIO0.13 13 14 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.13 1 P0INTPOLSET14 Interrupt Polarity-level set (high level or rising edge) of GPIO0.14 14 15 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.14 1 P0INTPOLSET15 Interrupt Polarity-level set (high level or rising edge) of GPIO0.15 15 16 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.15 1 P0INTPOLSET16 Interrupt Polarity-level set (high level or rising edge) of GPIO0.16 16 17 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.16 1 P0INTPOLSET17 Interrupt Polarity-level set (high level or rising edge) of GPIO0.17 17 18 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.17 1 P0INTPOLSET18 Interrupt Polarity-level set (high level or rising edge) of GPIO0.18 18 19 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.18 1 P0INTPOLSET19 Interrupt Polarity-level set (high level or rising edge) of GPIO0.19 19 20 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.19 1 P0INTPOLSET2 Interrupt Polarity-level set (high level or rising edge) of GPIO0.2 2 3 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.2 1 P0INTPOLSET20 Interrupt Polarity-level set (high level or rising edge) of GPIO0.20 20 21 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.20 1 P0INTPOLSET21 Interrupt Polarity-level set (high level or rising edge) of GPIO0.21 21 22 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.21 1 P0INTPOLSET22 Interrupt Polarity-level set (high level or rising edge) of GPIO0.22 22 23 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.22 1 P0INTPOLSET23 Interrupt Polarity-level set (high level or rising edge) of GPIO0.23 23 24 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.23 1 P0INTPOLSET3 Interrupt Polarity-level set (high level or rising edge) of GPIO0.3 3 4 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.3 1 P0INTPOLSET4 Interrupt Polarity-level set (high level or rising edge) of GPIO0.4 4 5 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.4 1 P0INTPOLSET5 Interrupt Polarity-level set (high level or rising edge) of GPIO0.5 5 6 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.5 1 P0INTPOLSET6 Interrupt Polarity-level set (high level or rising edge) of GPIO0.6 6 7 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.6 1 P0INTPOLSET7 Interrupt Polarity-level set (high level or rising edge) of GPIO0.7 7 8 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.7 1 P0INTPOLSET8 Interrupt Polarity-level set (high level or rising edge) of GPIO0.8 8 9 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.8 1 P0INTPOLSET9 Interrupt Polarity-level set (high level or rising edge) of GPIO0.9 9 10 read-write 0 No effect 0 1 Interrupt Polarity-level set (high level or rising edge) of GPIO0.9 1 P0INTSTATUS Port 0 Interrupt Request Status Register 0x38 32 read-write n 0x0 0xFFFFFF P0INTSTATUS0 Clear interrupt request status of GPIO0.0 0 1 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.0 1 P0INTSTATUS1 Clear interrupt request status of GPIO0.1 1 2 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.1 1 P0INTSTATUS10 Clear interrupt request status of GPIO0.10 10 11 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.10 1 P0INTSTATUS11 Clear interrupt request status of GPIO0.11 11 12 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.11 1 P0INTSTATUS12 Clear interrupt request status of GPIO0.12 12 13 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.12 1 P0INTSTATUS13 Clear interrupt request status of GPIO0.13 13 14 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.13 1 P0INTSTATUS14 Clear interrupt request status of GPIO0.14 14 15 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.14 1 P0INTSTATUS15 Clear interrupt request status of GPIO0.15 15 16 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.15 1 P0INTSTATUS16 Clear interrupt request status of GPIO0.16 16 17 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.16 1 P0INTSTATUS17 Clear interrupt request status of GPIO0.17 17 18 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.17 1 P0INTSTATUS18 Clear interrupt request status of GPIO0.18 18 19 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.18 1 P0INTSTATUS19 Clear interrupt request status of GPIO0.19 19 20 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.19 1 P0INTSTATUS2 Clear interrupt request status of GPIO0.2 2 3 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.2 1 P0INTSTATUS20 Clear interrupt request status of GPIO0.20 20 21 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.20 1 P0INTSTATUS21 Clear interrupt request status of GPIO0.21 21 22 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.21 1 P0INTSTATUS22 Clear interrupt request status of GPIO0.22 22 23 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.22 1 P0INTSTATUS23 Clear interrupt request status of GPIO0.23 23 24 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.23 1 P0INTSTATUS3 Clear interrupt request status of GPIO0.3 3 4 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.3 1 P0INTSTATUS4 Clear interrupt request status of GPIO0.4 4 5 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.4 1 P0INTSTATUS5 Clear interrupt request status of GPIO0.5 5 6 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.5 1 P0INTSTATUS6 Clear interrupt request status of GPIO0.6 6 7 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.6 1 P0INTSTATUS7 Clear interrupt request status of GPIO0.7 7 8 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.7 1 P0INTSTATUS8 Clear interrupt request status of GPIO0.8 8 9 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.8 1 P0INTSTATUS9 Clear interrupt request status of GPIO0.9 9 10 read-write 0 No effect 0 1 Clear interrupt request status of GPIO0.9 1 P0INTTYPECLR Port 0 Interrupt Type Clear Register 0x2C 32 read-write n 0x0 0xFFFFFF P0INTTYPECLR0 Interrupt type clean (interrupt by level) of GPIO0.0 0 1 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.0 1 P0INTTYPECLR1 Interrupt type clean (interrupt by level) of GPIO0.1 1 2 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.1 1 P0INTTYPECLR10 Interrupt type clean (interrupt by level) of GPIO0.10 10 11 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.10 1 P0INTTYPECLR11 Interrupt type clean (interrupt by level) of GPIO0.11 11 12 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.11 1 P0INTTYPECLR12 Interrupt type clean (interrupt by level) of GPIO0.12 12 13 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.12 1 P0INTTYPECLR13 Interrupt type clean (interrupt by level) of GPIO0.13 13 14 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.13 1 P0INTTYPECLR14 Interrupt type clean (interrupt by level) of GPIO0.14 14 15 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.14 1 P0INTTYPECLR15 Interrupt type clean (interrupt by level) of GPIO0.15 15 16 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.15 1 P0INTTYPECLR16 Interrupt type clean (interrupt by level) of GPIO0.16 16 17 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.16 1 P0INTTYPECLR17 Interrupt type clean (interrupt by level) of GPIO0.17 17 18 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.17 1 P0INTTYPECLR18 Interrupt type clean (interrupt by level) of GPIO0.18 18 19 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.18 1 P0INTTYPECLR19 Interrupt type clean (interrupt by level) of GPIO0.19 19 20 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.19 1 P0INTTYPECLR2 Interrupt type clean (interrupt by level) of GPIO0.2 2 3 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.2 1 P0INTTYPECLR20 Interrupt type clean (interrupt by level) of GPIO0.20 20 21 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.20 1 P0INTTYPECLR21 Interrupt type clean (interrupt by level) of GPIO0.21 21 22 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.21 1 P0INTTYPECLR22 Interrupt type clean (interrupt by level) of GPIO0.22 22 23 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.22 1 P0INTTYPECLR23 Interrupt type clean (interrupt by level) of GPIO0.23 23 24 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.23 1 P0INTTYPECLR3 Interrupt type clean (interrupt by level) of GPIO0.3 3 4 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.3 1 P0INTTYPECLR4 Interrupt type clean (interrupt by level) of GPIO0.4 4 5 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.4 1 P0INTTYPECLR5 Interrupt type clean (interrupt by level) of GPIO0.5 5 6 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.5 1 P0INTTYPECLR6 Interrupt type clean (interrupt by level) of GPIO0.6 6 7 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.6 1 P0INTTYPECLR7 Interrupt type clean (interrupt by level) of GPIO0.7 7 8 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.7 1 P0INTTYPECLR8 Interrupt type clean (interrupt by level) of GPIO0.8 8 9 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.8 1 P0INTTYPECLR9 Interrupt type clean (interrupt by level) of GPIO0.9 9 10 read-write 0 No effect 0 1 Interrupt type clean (interrupt by level) of GPIO0.9 1 P0INTTYPESET Port 0 Interrupt Type Set Register 0x28 32 read-write n 0x0 0xFFFFFF P0INTTYPESET0 Interrupt type set (interrupt by edge) of GPIO0.0 0 1 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.0 1 P0INTTYPESET1 Interrupt type set (interrupt by edge) of GPIO0.1 1 2 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.1 1 P0INTTYPESET10 Interrupt type set (interrupt by edge) of GPIO0.10 10 11 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.10 1 P0INTTYPESET11 Interrupt type set (interrupt by edge) of GPIO0.11 11 12 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.11 1 P0INTTYPESET12 Interrupt type set (interrupt by edge) of GPIO0.12 12 13 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.12 1 P0INTTYPESET13 Interrupt type set (interrupt by edge) of GPIO0.13 13 14 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.13 1 P0INTTYPESET14 Interrupt type set (interrupt by edge) of GPIO0.14 14 15 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.14 1 P0INTTYPESET15 Interrupt type set (interrupt by edge) of GPIO0.15 15 16 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.15 1 P0INTTYPESET16 Interrupt type set (interrupt by edge) of GPIO0.16 16 17 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.16 1 P0INTTYPESET17 Interrupt type set (interrupt by edge) of GPIO0.17 17 18 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.17 1 P0INTTYPESET18 Interrupt type set (interrupt by edge) of GPIO0.18 18 19 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.18 1 P0INTTYPESET19 Interrupt type set (interrupt by edge) of GPIO0.19 19 20 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.19 1 P0INTTYPESET2 Interrupt type set (interrupt by edge) of GPIO0.2 2 3 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.2 1 P0INTTYPESET20 Interrupt type set (interrupt by edge) of GPIO0.20 20 21 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.20 1 P0INTTYPESET21 Interrupt type set (interrupt by edge) of GPIO0.21 21 22 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.21 1 P0INTTYPESET22 Interrupt type set (interrupt by edge) of GPIO0.22 22 23 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.22 1 P0INTTYPESET23 Interrupt type set (interrupt by edge) of GPIO0.23 23 24 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.23 1 P0INTTYPESET3 Interrupt type set (interrupt by edge) of GPIO0.3 3 4 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.3 1 P0INTTYPESET4 Interrupt type set (interrupt by edge) of GPIO0.4 4 5 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.4 1 P0INTTYPESET5 Interrupt type set (interrupt by edge) of GPIO0.5 5 6 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.5 1 P0INTTYPESET6 Interrupt type set (interrupt by edge) of GPIO0.6 6 7 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.6 1 P0INTTYPESET7 Interrupt type set (interrupt by edge) of GPIO0.7 7 8 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.7 1 P0INTTYPESET8 Interrupt type set (interrupt by edge) of GPIO0.8 8 9 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.8 1 P0INTTYPESET9 Interrupt type set (interrupt by edge) of GPIO0.9 9 10 read-write 0 No effect 0 1 Interrupt type set (interrupt by edge) of GPIO0.9 1 P0OUTENABLECLR Port 0 Output Enable Clear Register 0x14 32 read-write n 0x0 0xFFFFFF P0OUTENABLECLR0 0 Output Enable Clear of GPIO0.0 0 1 read-write 0 No effect 0 1 Output enable clear of GPIO0.0 1 P0OUTENABLECLR1 Output Enable Clear of GPIO0.1 1 2 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.1 1 P0OUTENABLECLR10 Output Enable Clear of GPIO0.10 10 11 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.10 1 P0OUTENABLECLR11 Output Enable Clear of GPIO0.11 11 12 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.11 1 P0OUTENABLECLR12 Output Enable Clear of GPIO0.12 12 13 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.12 1 P0OUTENABLECLR13 Output Enable Clear of GPIO0.13 13 14 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.13 1 P0OUTENABLECLR14 Output Enable Clear of GPIO0.14 14 15 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.14 1 P0OUTENABLECLR15 Output Enable Clear of GPIO0.15 15 16 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.15 1 P0OUTENABLECLR16 Output Enable Clear of GPIO0.16 16 17 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.16 1 P0OUTENABLECLR17 Output Enable Clear of GPIO0.17 17 18 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.17 1 P0OUTENABLECLR18 Output Enable Clear of GPIO0.18 18 19 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.18 1 P0OUTENABLECLR19 Output Enable Clear of GPIO0.19 19 20 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.19 1 P0OUTENABLECLR2 Output Enable Clear of GPIO0.2 2 3 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.2 1 P0OUTENABLECLR20 Output Enable Clear of GPIO0.20 20 21 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.20 1 P0OUTENABLECLR21 Output Enable Clear of GPIO0.21 21 22 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.21 1 P0OUTENABLECLR22 Output Enable Clear of GPIO0.22 22 23 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.22 1 P0OUTENABLECLR23 Output Enable Clear of GPIO0.23 23 24 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.23 1 P0OUTENABLECLR3 Output Enable Clear of GPIO0.3 3 4 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.3 1 P0OUTENABLECLR4 Output Enable Clear of GPIO0.4 4 5 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.4 1 P0OUTENABLECLR5 Output Enable Clear of GPIO0.5 5 6 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.5 1 P0OUTENABLECLR6 Output Enable Clear of GPIO0.6 6 7 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.6 1 P0OUTENABLECLR7 Output Enable Clear of GPIO0.7 7 8 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.7 1 P0OUTENABLECLR8 Output Enable Clear of GPIO0.8 8 9 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.8 1 P0OUTENABLECLR9 Output Enable Clear of GPIO0.9 9 10 read-write 0 No effect 0 1 Output Enable Clear of GPIO0.9 1 P0OUTENABLESET Port 0 Output Enable Set Register 0x10 32 read-write n 0x0 0xFFFFFF P0OUTENABLESET0 Output Enable Set of GPIO0.0 0 1 read-write 0 No effect 0 1 Output Enable Set of GPIO0.0 1 P0OUTENABLESET1 Output Enable Set of GPIO0.1 1 2 read-write 0 No effect 0 1 Output Enable Set of GPIO0.1 1 P0OUTENABLESET10 Output Enable Set of GPIO0.10 10 11 read-write 0 No effect 0 1 Output Enable Set of GPIO0.10 1 P0OUTENABLESET11 Output Enable Set of GPIO0.11 11 12 read-write 0 No effect 0 1 Output Enable Set of GPIO0.11 1 P0OUTENABLESET12 Output Enable Set of GPIO0.12 12 13 read-write 0 No effect 0 1 Output Enable Set of GPIO0.12 1 P0OUTENABLESET13 Output Enable Set of GPIO0.13 13 14 read-write 0 No effect 0 1 Output Enable Set of GPIO0.13 1 P0OUTENABLESET14 Output Enable Set of GPIO0.14 14 15 read-write 0 No effect 0 1 Output Enable Set of GPIO0.14 1 P0OUTENABLESET15 Output Enable Set of GPIO0.15 15 16 read-write 0 No effect 0 1 Output Enable Set of GPIO0.15 1 P0OUTENABLESET16 Output Enable Set of GPIO0.16 16 17 read-write 0 No effect 0 1 Output Enable Set of GPIO0.16 1 P0OUTENABLESET17 Output Enable Set of GPIO0.17 17 18 read-write 0 No effect 0 1 Output Enable Set of GPIO0.17 1 P0OUTENABLESET18 Output Enable Set of GPIO0.18 18 19 read-write 0 No effect 0 1 Output Enable Set of GPIO0.18 1 P0OUTENABLESET19 Output Enable Set of GPIO0.19 19 20 read-write 0 No effect 0 1 Output Enable Set of GPIO0.19 1 P0OUTENABLESET2 Output Enable Set of GPIO0.2 2 3 read-write 0 No effect 0 1 Output Enable Set of GPIO0.2 1 P0OUTENABLESET20 Output Enable Set of GPIO0.20 20 21 read-write 0 No effect 0 1 Output Enable Set of GPIO0.20 1 P0OUTENABLESET21 Output Enable Set of GPIO0.21 21 22 read-write 0 No effect 0 1 Output Enable Set of GPIO0.21 1 P0OUTENABLESET22 Output Enable Set of GPIO0.22 22 23 read-write 0 No effect 0 1 Output Enable Set of GPIO0.22 1 P0OUTENABLESET23 Output Enable Set of GPIO0.23 23 24 read-write 0 No effect 0 1 Output Enable Set of GPIO0.23 1 P0OUTENABLESET3 Output Enable Set of GPIO0.3 3 4 read-write 0 No effect 0 1 Output Enable Set of GPIO0.3 1 P0OUTENABLESET4 Output Enable Set of GPIO0.4 4 5 read-write 0 No effect 0 1 Output Enable Set of GPIO0.4 1 P0OUTENABLESET5 Output Enable Set of GPIO0.5 5 6 read-write 0 No effect 0 1 Output Enable Set of GPIO0.5 1 P0OUTENABLESET6 Output Enable Set of GPIO0.6 6 7 read-write 0 No effect 0 1 Output Enable Set of GPIO0.6 1 P0OUTENABLESET7 Output Enable Set of GPIO0.7 7 8 read-write 0 No effect 0 1 Output Enable Set of GPIO0.7 1 P0OUTENABLESET8 Output Enable Set of GPIO0.8 8 9 read-write 0 No effect 0 1 Output Enable Set of GPIO0.8 1 P0OUTENABLESET9 Output Enable Set of GPIO0.9 9 10 read-write 0 No effect 0 1 Output Enable Set of GPIO0.9 1 P0PUN Port 0 Pull Up Not Register 0x8 32 read-write n 0x0 0xFFFFFF P0PUN0 Pull Up of GPIO0.0 0 1 read-write 0 Pull Up of GPIO0.0 is enable 0 1 Pull Up of GPIO0.0 is disable 1 P0PUN1 Pull Up of GPIO0.1 1 2 read-write 0 Pull Up of GPIO0.1 is enable 0 1 Pull Up of GPIO0.1 is disable 1 P0PUN10 Pull Up of GPIO0.10 10 11 read-write 0 Pull Up of GPIO0.10 is enable 0 1 Pull Up of GPIO0.10 is disable 1 P0PUN11 Pull Up of GPIO0.11 11 12 read-write 0 Pull Up of GPIO0.11 is enable 0 1 Pull Up of GPIO0.11 is disable 1 P0PUN12 Pull Up of GPIO0.12 12 13 read-write 0 Pull Up of GPIO0.12 is enable 0 1 Pull Up of GPIO0.12 is disable 1 P0PUN13 Pull Up of GPIO0.13 13 14 read-write 0 Pull Up of GPIO0.13 is enable 0 1 Pull Up of GPIO0.13 is disable 1 P0PUN14 Pull Up of GPIO0.14 14 15 read-write 0 Pull Up of GPIO0.14 is enable 0 1 Pull Up of GPIO0.14 is disable 1 P0PUN15 Pull Up of GPIO0.15 15 16 read-write 0 Pull Up of GPIO0.15 is enable 0 1 Pull Up of GPIO0.15 is disable 1 P0PUN16 Pull Up of GPIO0.16 16 17 read-write 0 Pull Up of GPIO0.16 is enable 0 1 Pull Up of GPIO0.16 is disable 1 P0PUN17 Pull Up of GPIO0.17 17 18 read-write 0 Pull Up of GPIO0.17 is enable 0 1 Pull Up of GPIO0.17 is disable 1 P0PUN18 Pull Up of GPIO0.18 18 19 read-write 0 Pull Up of GPIO0.18 is enable 0 1 Pull Up of GPIO0.18 is disable 1 P0PUN19 Pull Up of GPIO0.19 19 20 read-write 0 Pull Up of GPIO0.19 is enable 0 1 Pull Up of GPIO0.19 is disable 1 P0PUN2 Pull Up of GPIO0.2 2 3 read-write 0 Pull Up of GPIO0.2 is enable 0 1 Pull Up of GPIO0.2 is disable 1 P0PUN20 Pull Up of GPIO0.20 20 21 read-write 0 Pull Up of GPIO0.20 is enable 0 1 Pull Up of GPIO0.20 is disable 1 P0PUN21 Pull Up of GPIO0.21 21 22 read-write 0 Pull Up of GPIO0.21 is enable 0 1 Pull Up of GPIO0.21 is disable 1 P0PUN22 Pull Up of GPIO0.22 22 23 read-write 0 Pull Up of GPIO0.22 is enable 0 1 Pull Up of GPIO0.22 is disable 1 P0PUN23 Pull Up of GPIO0.23 23 24 read-write 0 Pull Up of GPIO0.23 is enable 0 1 Pull Up of GPIO0.23 is disable 1 P0PUN3 Pull Up of GPIO0.3 3 4 read-write 0 Pull Up of GPIO0.3 is enable 0 1 Pull Up of GPIO0.3 is disable 1 P0PUN4 Pull Up of GPIO0.4 4 5 read-write 0 Pull Up of GPIO0.4 is enable 0 1 Pull Up of GPIO0.4 is disable 1 P0PUN5 Pull Up of GPIO0.5 5 6 read-write 0 Pull Up of GPIO0.5 is enable 0 1 Pull Up of GPIO0.5 is disable 1 P0PUN6 Pull Up of GPIO0.6 6 7 read-write 0 Pull Up of GPIO0.6 is enable 0 1 Pull Up of GPIO0.6 is disable 1 P0PUN7 Pull Up of GPIO0.7 7 8 read-write 0 Pull Up of GPIO0.7 is enable 0 1 Pull Up of GPIO0.7 is disable 1 P0PUN8 Pull Up of GPIO0.8 8 9 read-write 0 Pull Up of GPIO0.8 is enable 0 1 Pull Up of GPIO0.8 is disable 1 P0PUN9 Pull Up of GPIO0.9 9 10 read-write 0 Pull Up of GPIO0.9 is enable 0 1 Pull Up of GPIO0.9 is disable 1 P0PUN_PIN Port 0 Pull Up Not Register access by Pin P0PUN 0x8 32 read-write n 0x0 0xFFFFFF P0WUN Port 0 Wakeup Enable Not Register 0xC 32 read-write n 0x0 0xFFFFFF P0WUN0 Wakeup of GPIO0.0 0 1 read-write 0 Wakeup of GPIO0.0 is enable 0 1 Wakeup of GPIO0.0 is disable 1 P0WUN1 Wakeup of GPIO0.1 1 2 read-write 0 Wakeup of GPIO0.1 is enable 0 1 Wakeup of GPIO0.1 is disable 1 P0WUN10 Wakeup of GPIO0.10 10 11 read-write 0 Wakeup of GPIO0.10 is enable 0 1 Wakeup of GPIO0.10 is disable 1 P0WUN11 Wakeup of GPIO0.11 11 12 read-write 0 Wakeup of GPIO0.11 is enable 0 1 Wakeup of GPIO0.11 is disable 1 P0WUN12 Wakeup of GPIO0.12 12 13 read-write 0 Wakeup of GPIO0.12 is enable 0 1 Wakeup of GPIO0.12 is disable 1 P0WUN13 Wakeup of GPIO0.13 13 14 read-write 0 Wakeup of GPIO0.13 is enable 0 1 Wakeup of GPIO0.13 is disable 1 P0WUN14 Wakeup of GPIO0.14 14 15 read-write 0 Wakeup of GPIO0.14 is enable 0 1 Wakeup of GPIO0.14 is disable 1 P0WUN15 Wakeup of GPIO0.15 15 16 read-write 0 Wakeup of GPIO0.15 is enable 0 1 Wakeup of GPIO0.15 is disable 1 P0WUN16 Wakeup of GPIO0.16 16 17 read-write 0 Wakeup of GPIO0.16 is enable 0 1 Wakeup of GPIO0.16 is disable 1 P0WUN17 Wakeup of GPIO0.17 17 18 read-write 0 Wakeup of GPIO0.17 is enable 0 1 Wakeup of GPIO0.17 is disable 1 P0WUN18 Wakeup of GPIO0.18 18 19 read-write 0 Wakeup of GPIO0.18 is enable 0 1 Wakeup of GPIO0.18 is disable 1 P0WUN19 Wakeup of GPIO0.19 19 20 read-write 0 Wakeup of GPIO0.19 is enable 0 1 Wakeup of GPIO0.19 is disable 1 P0WUN2 Wakeup of GPIO0.2 2 3 read-write 0 Wakeup of GPIO0.2 is enable 0 1 Wakeup of GPIO0.2 is disable 1 P0WUN20 Wakeup of GPIO0.20 20 21 read-write 0 Wakeup of GPIO0.20 is enable 0 1 Wakeup of GPIO0.20 is disable 1 P0WUN21 Wakeup of GPIO0.21 21 22 read-write 0 Wakeup of GPIO0.21 is enable 0 1 Wakeup of GPIO0.21 is disable 1 P0WUN22 Wakeup of GPIO0.22 22 23 read-write 0 Wakeup of GPIO0.22 is enable 0 1 Wakeup of GPIO0.22 is disable 1 P0WUN23 Wakeup of GPIO0.23 23 24 read-write 0 Wakeup of GPIO0.23 is enable 0 1 Wakeup of GPIO0.23 is disable 1 P0WUN3 Wakeup of GPIO0.3 3 4 read-write 0 Wakeup of GPIO0.3 is enable 0 1 Wakeup of GPIO0.3 is disable 1 P0WUN4 Wakeup of GPIO0.4 4 5 read-write 0 Wakeup of GPIO0.4 is enable 0 1 Wakeup of GPIO0.4 is disable 1 P0WUN5 Wakeup of GPIO0.5 5 6 read-write 0 Wakeup of GPIO0.5 is enable 0 1 Wakeup of GPIO0.5 is disable 1 P0WUN6 Wakeup of GPIO0.6 6 7 read-write 0 Wakeup of GPIO0.6 is enable 0 1 Wakeup of GPIO0.6 is disable 1 P0WUN7 Wakeup of GPIO0.7 7 8 read-write 0 Wakeup of GPIO0.7 is enable 0 1 Wakeup of GPIO0.7 is disable 1 P0WUN8 Wakeup of GPIO0.8 8 9 read-write 0 Wakeup of GPIO0.8 is enable 0 1 Wakeup of GPIO0.8 is disable 1 P0WUN9 Wakeup of GPIO0.9 9 10 read-write 0 Wakeup of GPIO0.9 is enable 0 1 Wakeup of GPIO0.9 is disable 1 P0WUN_PIN Port 0 Wakeup Enable Not Register access by Pin P0WUN 0xC 32 read-write n 0x0 0xFFFFFF UB_MASKED0 Upper byte Masked Access Register 0x800 32 read-write n 0x0 0xFFFFFFFF UB_MASKED1 Upper byte Masked Access Register 0x804 32 read-write n 0x0 0xFFFFFFFF UB_MASKED10 Upper byte Masked Access Register 0x828 32 read-write n 0x0 0xFFFFFFFF UB_MASKED100 Upper byte Masked Access Register 0x990 32 read-write n 0x0 0xFFFFFFFF UB_MASKED101 Upper byte Masked Access Register 0x994 32 read-write n 0x0 0xFFFFFFFF UB_MASKED102 Upper byte Masked Access Register 0x998 32 read-write n 0x0 0xFFFFFFFF UB_MASKED103 Upper byte Masked Access Register 0x99C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED104 Upper byte Masked Access Register 0x9A0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED105 Upper byte Masked Access Register 0x9A4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED106 Upper byte Masked Access Register 0x9A8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED107 Upper byte Masked Access Register 0x9AC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED108 Upper byte Masked Access Register 0x9B0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED109 Upper byte Masked Access Register 0x9B4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED11 Upper byte Masked Access Register 0x82C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED110 Upper byte Masked Access Register 0x9B8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED111 Upper byte Masked Access Register 0x9BC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED112 Upper byte Masked Access Register 0x9C0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED113 Upper byte Masked Access Register 0x9C4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED114 Upper byte Masked Access Register 0x9C8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED115 Upper byte Masked Access Register 0x9CC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED116 Upper byte Masked Access Register 0x9D0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED117 Upper byte Masked Access Register 0x9D4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED118 Upper byte Masked Access Register 0x9D8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED119 Upper byte Masked Access Register 0x9DC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED12 Upper byte Masked Access Register 0x830 32 read-write n 0x0 0xFFFFFFFF UB_MASKED120 Upper byte Masked Access Register 0x9E0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED121 Upper byte Masked Access Register 0x9E4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED122 Upper byte Masked Access Register 0x9E8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED123 Upper byte Masked Access Register 0x9EC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED124 Upper byte Masked Access Register 0x9F0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED125 Upper byte Masked Access Register 0x9F4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED126 Upper byte Masked Access Register 0x9F8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED127 Upper byte Masked Access Register 0x9FC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED128 Upper byte Masked Access Register 0xA00 32 read-write n 0x0 0xFFFFFFFF UB_MASKED129 Upper byte Masked Access Register 0xA04 32 read-write n 0x0 0xFFFFFFFF UB_MASKED13 Upper byte Masked Access Register 0x834 32 read-write n 0x0 0xFFFFFFFF UB_MASKED130 Upper byte Masked Access Register 0xA08 32 read-write n 0x0 0xFFFFFFFF UB_MASKED131 Upper byte Masked Access Register 0xA0C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED132 Upper byte Masked Access Register 0xA10 32 read-write n 0x0 0xFFFFFFFF UB_MASKED133 Upper byte Masked Access Register 0xA14 32 read-write n 0x0 0xFFFFFFFF UB_MASKED134 Upper byte Masked Access Register 0xA18 32 read-write n 0x0 0xFFFFFFFF UB_MASKED135 Upper byte Masked Access Register 0xA1C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED136 Upper byte Masked Access Register 0xA20 32 read-write n 0x0 0xFFFFFFFF UB_MASKED137 Upper byte Masked Access Register 0xA24 32 read-write n 0x0 0xFFFFFFFF UB_MASKED138 Upper byte Masked Access Register 0xA28 32 read-write n 0x0 0xFFFFFFFF UB_MASKED139 Upper byte Masked Access Register 0xA2C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED14 Upper byte Masked Access Register 0x838 32 read-write n 0x0 0xFFFFFFFF UB_MASKED140 Upper byte Masked Access Register 0xA30 32 read-write n 0x0 0xFFFFFFFF UB_MASKED141 Upper byte Masked Access Register 0xA34 32 read-write n 0x0 0xFFFFFFFF UB_MASKED142 Upper byte Masked Access Register 0xA38 32 read-write n 0x0 0xFFFFFFFF UB_MASKED143 Upper byte Masked Access Register 0xA3C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED144 Upper byte Masked Access Register 0xA40 32 read-write n 0x0 0xFFFFFFFF UB_MASKED145 Upper byte Masked Access Register 0xA44 32 read-write n 0x0 0xFFFFFFFF UB_MASKED146 Upper byte Masked Access Register 0xA48 32 read-write n 0x0 0xFFFFFFFF UB_MASKED147 Upper byte Masked Access Register 0xA4C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED148 Upper byte Masked Access Register 0xA50 32 read-write n 0x0 0xFFFFFFFF UB_MASKED149 Upper byte Masked Access Register 0xA54 32 read-write n 0x0 0xFFFFFFFF UB_MASKED15 Upper byte Masked Access Register 0x83C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED150 Upper byte Masked Access Register 0xA58 32 read-write n 0x0 0xFFFFFFFF UB_MASKED151 Upper byte Masked Access Register 0xA5C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED152 Upper byte Masked Access Register 0xA60 32 read-write n 0x0 0xFFFFFFFF UB_MASKED153 Upper byte Masked Access Register 0xA64 32 read-write n 0x0 0xFFFFFFFF UB_MASKED154 Upper byte Masked Access Register 0xA68 32 read-write n 0x0 0xFFFFFFFF UB_MASKED155 Upper byte Masked Access Register 0xA6C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED156 Upper byte Masked Access Register 0xA70 32 read-write n 0x0 0xFFFFFFFF UB_MASKED157 Upper byte Masked Access Register 0xA74 32 read-write n 0x0 0xFFFFFFFF UB_MASKED158 Upper byte Masked Access Register 0xA78 32 read-write n 0x0 0xFFFFFFFF UB_MASKED159 Upper byte Masked Access Register 0xA7C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED16 Upper byte Masked Access Register 0x840 32 read-write n 0x0 0xFFFFFFFF UB_MASKED160 Upper byte Masked Access Register 0xA80 32 read-write n 0x0 0xFFFFFFFF UB_MASKED161 Upper byte Masked Access Register 0xA84 32 read-write n 0x0 0xFFFFFFFF UB_MASKED162 Upper byte Masked Access Register 0xA88 32 read-write n 0x0 0xFFFFFFFF UB_MASKED163 Upper byte Masked Access Register 0xA8C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED164 Upper byte Masked Access Register 0xA90 32 read-write n 0x0 0xFFFFFFFF UB_MASKED165 Upper byte Masked Access Register 0xA94 32 read-write n 0x0 0xFFFFFFFF UB_MASKED166 Upper byte Masked Access Register 0xA98 32 read-write n 0x0 0xFFFFFFFF UB_MASKED167 Upper byte Masked Access Register 0xA9C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED168 Upper byte Masked Access Register 0xAA0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED169 Upper byte Masked Access Register 0xAA4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED17 Upper byte Masked Access Register 0x844 32 read-write n 0x0 0xFFFFFFFF UB_MASKED170 Upper byte Masked Access Register 0xAA8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED171 Upper byte Masked Access Register 0xAAC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED172 Upper byte Masked Access Register 0xAB0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED173 Upper byte Masked Access Register 0xAB4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED174 Upper byte Masked Access Register 0xAB8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED175 Upper byte Masked Access Register 0xABC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED176 Upper byte Masked Access Register 0xAC0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED177 Upper byte Masked Access Register 0xAC4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED178 Upper byte Masked Access Register 0xAC8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED179 Upper byte Masked Access Register 0xACC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED18 Upper byte Masked Access Register 0x848 32 read-write n 0x0 0xFFFFFFFF UB_MASKED180 Upper byte Masked Access Register 0xAD0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED181 Upper byte Masked Access Register 0xAD4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED182 Upper byte Masked Access Register 0xAD8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED183 Upper byte Masked Access Register 0xADC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED184 Upper byte Masked Access Register 0xAE0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED185 Upper byte Masked Access Register 0xAE4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED186 Upper byte Masked Access Register 0xAE8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED187 Upper byte Masked Access Register 0xAEC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED188 Upper byte Masked Access Register 0xAF0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED189 Upper byte Masked Access Register 0xAF4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED19 Upper byte Masked Access Register 0x84C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED190 Upper byte Masked Access Register 0xAF8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED191 Upper byte Masked Access Register 0xAFC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED192 Upper byte Masked Access Register 0xB00 32 read-write n 0x0 0xFFFFFFFF UB_MASKED193 Upper byte Masked Access Register 0xB04 32 read-write n 0x0 0xFFFFFFFF UB_MASKED194 Upper byte Masked Access Register 0xB08 32 read-write n 0x0 0xFFFFFFFF UB_MASKED195 Upper byte Masked Access Register 0xB0C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED196 Upper byte Masked Access Register 0xB10 32 read-write n 0x0 0xFFFFFFFF UB_MASKED197 Upper byte Masked Access Register 0xB14 32 read-write n 0x0 0xFFFFFFFF UB_MASKED198 Upper byte Masked Access Register 0xB18 32 read-write n 0x0 0xFFFFFFFF UB_MASKED199 Upper byte Masked Access Register 0xB1C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED2 Upper byte Masked Access Register 0x808 32 read-write n 0x0 0xFFFFFFFF UB_MASKED20 Upper byte Masked Access Register 0x850 32 read-write n 0x0 0xFFFFFFFF UB_MASKED200 Upper byte Masked Access Register 0xB20 32 read-write n 0x0 0xFFFFFFFF UB_MASKED201 Upper byte Masked Access Register 0xB24 32 read-write n 0x0 0xFFFFFFFF UB_MASKED202 Upper byte Masked Access Register 0xB28 32 read-write n 0x0 0xFFFFFFFF UB_MASKED203 Upper byte Masked Access Register 0xB2C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED204 Upper byte Masked Access Register 0xB30 32 read-write n 0x0 0xFFFFFFFF UB_MASKED205 Upper byte Masked Access Register 0xB34 32 read-write n 0x0 0xFFFFFFFF UB_MASKED206 Upper byte Masked Access Register 0xB38 32 read-write n 0x0 0xFFFFFFFF UB_MASKED207 Upper byte Masked Access Register 0xB3C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED208 Upper byte Masked Access Register 0xB40 32 read-write n 0x0 0xFFFFFFFF UB_MASKED209 Upper byte Masked Access Register 0xB44 32 read-write n 0x0 0xFFFFFFFF UB_MASKED21 Upper byte Masked Access Register 0x854 32 read-write n 0x0 0xFFFFFFFF UB_MASKED210 Upper byte Masked Access Register 0xB48 32 read-write n 0x0 0xFFFFFFFF UB_MASKED211 Upper byte Masked Access Register 0xB4C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED212 Upper byte Masked Access Register 0xB50 32 read-write n 0x0 0xFFFFFFFF UB_MASKED213 Upper byte Masked Access Register 0xB54 32 read-write n 0x0 0xFFFFFFFF UB_MASKED214 Upper byte Masked Access Register 0xB58 32 read-write n 0x0 0xFFFFFFFF UB_MASKED215 Upper byte Masked Access Register 0xB5C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED216 Upper byte Masked Access Register 0xB60 32 read-write n 0x0 0xFFFFFFFF UB_MASKED217 Upper byte Masked Access Register 0xB64 32 read-write n 0x0 0xFFFFFFFF UB_MASKED218 Upper byte Masked Access Register 0xB68 32 read-write n 0x0 0xFFFFFFFF UB_MASKED219 Upper byte Masked Access Register 0xB6C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED22 Upper byte Masked Access Register 0x858 32 read-write n 0x0 0xFFFFFFFF UB_MASKED220 Upper byte Masked Access Register 0xB70 32 read-write n 0x0 0xFFFFFFFF UB_MASKED221 Upper byte Masked Access Register 0xB74 32 read-write n 0x0 0xFFFFFFFF UB_MASKED222 Upper byte Masked Access Register 0xB78 32 read-write n 0x0 0xFFFFFFFF UB_MASKED223 Upper byte Masked Access Register 0xB7C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED224 Upper byte Masked Access Register 0xB80 32 read-write n 0x0 0xFFFFFFFF UB_MASKED225 Upper byte Masked Access Register 0xB84 32 read-write n 0x0 0xFFFFFFFF UB_MASKED226 Upper byte Masked Access Register 0xB88 32 read-write n 0x0 0xFFFFFFFF UB_MASKED227 Upper byte Masked Access Register 0xB8C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED228 Upper byte Masked Access Register 0xB90 32 read-write n 0x0 0xFFFFFFFF UB_MASKED229 Upper byte Masked Access Register 0xB94 32 read-write n 0x0 0xFFFFFFFF UB_MASKED23 Upper byte Masked Access Register 0x85C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED230 Upper byte Masked Access Register 0xB98 32 read-write n 0x0 0xFFFFFFFF UB_MASKED231 Upper byte Masked Access Register 0xB9C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED232 Upper byte Masked Access Register 0xBA0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED233 Upper byte Masked Access Register 0xBA4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED234 Upper byte Masked Access Register 0xBA8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED235 Upper byte Masked Access Register 0xBAC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED236 Upper byte Masked Access Register 0xBB0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED237 Upper byte Masked Access Register 0xBB4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED238 Upper byte Masked Access Register 0xBB8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED239 Upper byte Masked Access Register 0xBBC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED24 Upper byte Masked Access Register 0x860 32 read-write n 0x0 0xFFFFFFFF UB_MASKED240 Upper byte Masked Access Register 0xBC0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED241 Upper byte Masked Access Register 0xBC4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED242 Upper byte Masked Access Register 0xBC8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED243 Upper byte Masked Access Register 0xBCC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED244 Upper byte Masked Access Register 0xBD0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED245 Upper byte Masked Access Register 0xBD4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED246 Upper byte Masked Access Register 0xBD8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED247 Upper byte Masked Access Register 0xBDC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED248 Upper byte Masked Access Register 0xBE0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED249 Upper byte Masked Access Register 0xBE4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED25 Upper byte Masked Access Register 0x864 32 read-write n 0x0 0xFFFFFFFF UB_MASKED250 Upper byte Masked Access Register 0xBE8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED251 Upper byte Masked Access Register 0xBEC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED252 Upper byte Masked Access Register 0xBF0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED253 Upper byte Masked Access Register 0xBF4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED254 Upper byte Masked Access Register 0xBF8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED255 Upper byte Masked Access Register 0xBFC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED26 Upper byte Masked Access Register 0x868 32 read-write n 0x0 0xFFFFFFFF UB_MASKED27 Upper byte Masked Access Register 0x86C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED28 Upper byte Masked Access Register 0x870 32 read-write n 0x0 0xFFFFFFFF UB_MASKED29 Upper byte Masked Access Register 0x874 32 read-write n 0x0 0xFFFFFFFF UB_MASKED3 Upper byte Masked Access Register 0x80C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED30 Upper byte Masked Access Register 0x878 32 read-write n 0x0 0xFFFFFFFF UB_MASKED31 Upper byte Masked Access Register 0x87C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED32 Upper byte Masked Access Register 0x880 32 read-write n 0x0 0xFFFFFFFF UB_MASKED33 Upper byte Masked Access Register 0x884 32 read-write n 0x0 0xFFFFFFFF UB_MASKED34 Upper byte Masked Access Register 0x888 32 read-write n 0x0 0xFFFFFFFF UB_MASKED35 Upper byte Masked Access Register 0x88C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED36 Upper byte Masked Access Register 0x890 32 read-write n 0x0 0xFFFFFFFF UB_MASKED37 Upper byte Masked Access Register 0x894 32 read-write n 0x0 0xFFFFFFFF UB_MASKED38 Upper byte Masked Access Register 0x898 32 read-write n 0x0 0xFFFFFFFF UB_MASKED39 Upper byte Masked Access Register 0x89C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED4 Upper byte Masked Access Register 0x810 32 read-write n 0x0 0xFFFFFFFF UB_MASKED40 Upper byte Masked Access Register 0x8A0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED41 Upper byte Masked Access Register 0x8A4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED42 Upper byte Masked Access Register 0x8A8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED43 Upper byte Masked Access Register 0x8AC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED44 Upper byte Masked Access Register 0x8B0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED45 Upper byte Masked Access Register 0x8B4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED46 Upper byte Masked Access Register 0x8B8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED47 Upper byte Masked Access Register 0x8BC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED48 Upper byte Masked Access Register 0x8C0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED49 Upper byte Masked Access Register 0x8C4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED5 Upper byte Masked Access Register 0x814 32 read-write n 0x0 0xFFFFFFFF UB_MASKED50 Upper byte Masked Access Register 0x8C8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED51 Upper byte Masked Access Register 0x8CC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED52 Upper byte Masked Access Register 0x8D0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED53 Upper byte Masked Access Register 0x8D4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED54 Upper byte Masked Access Register 0x8D8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED55 Upper byte Masked Access Register 0x8DC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED56 Upper byte Masked Access Register 0x8E0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED57 Upper byte Masked Access Register 0x8E4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED58 Upper byte Masked Access Register 0x8E8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED59 Upper byte Masked Access Register 0x8EC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED6 Upper byte Masked Access Register 0x818 32 read-write n 0x0 0xFFFFFFFF UB_MASKED60 Upper byte Masked Access Register 0x8F0 32 read-write n 0x0 0xFFFFFFFF UB_MASKED61 Upper byte Masked Access Register 0x8F4 32 read-write n 0x0 0xFFFFFFFF UB_MASKED62 Upper byte Masked Access Register 0x8F8 32 read-write n 0x0 0xFFFFFFFF UB_MASKED63 Upper byte Masked Access Register 0x8FC 32 read-write n 0x0 0xFFFFFFFF UB_MASKED64 Upper byte Masked Access Register 0x900 32 read-write n 0x0 0xFFFFFFFF UB_MASKED65 Upper byte Masked Access Register 0x904 32 read-write n 0x0 0xFFFFFFFF UB_MASKED66 Upper byte Masked Access Register 0x908 32 read-write n 0x0 0xFFFFFFFF UB_MASKED67 Upper byte Masked Access Register 0x90C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED68 Upper byte Masked Access Register 0x910 32 read-write n 0x0 0xFFFFFFFF UB_MASKED69 Upper byte Masked Access Register 0x914 32 read-write n 0x0 0xFFFFFFFF UB_MASKED7 Upper byte Masked Access Register 0x81C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED70 Upper byte Masked Access Register 0x918 32 read-write n 0x0 0xFFFFFFFF UB_MASKED71 Upper byte Masked Access Register 0x91C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED72 Upper byte Masked Access Register 0x920 32 read-write n 0x0 0xFFFFFFFF UB_MASKED73 Upper byte Masked Access Register 0x924 32 read-write n 0x0 0xFFFFFFFF UB_MASKED74 Upper byte Masked Access Register 0x928 32 read-write n 0x0 0xFFFFFFFF UB_MASKED75 Upper byte Masked Access Register 0x92C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED76 Upper byte Masked Access Register 0x930 32 read-write n 0x0 0xFFFFFFFF UB_MASKED77 Upper byte Masked Access Register 0x934 32 read-write n 0x0 0xFFFFFFFF UB_MASKED78 Upper byte Masked Access Register 0x938 32 read-write n 0x0 0xFFFFFFFF UB_MASKED79 Upper byte Masked Access Register 0x93C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED8 Upper byte Masked Access Register 0x820 32 read-write n 0x0 0xFFFFFFFF UB_MASKED80 Upper byte Masked Access Register 0x940 32 read-write n 0x0 0xFFFFFFFF UB_MASKED81 Upper byte Masked Access Register 0x944 32 read-write n 0x0 0xFFFFFFFF UB_MASKED82 Upper byte Masked Access Register 0x948 32 read-write n 0x0 0xFFFFFFFF UB_MASKED83 Upper byte Masked Access Register 0x94C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED84 Upper byte Masked Access Register 0x950 32 read-write n 0x0 0xFFFFFFFF UB_MASKED85 Upper byte Masked Access Register 0x954 32 read-write n 0x0 0xFFFFFFFF UB_MASKED86 Upper byte Masked Access Register 0x958 32 read-write n 0x0 0xFFFFFFFF UB_MASKED87 Upper byte Masked Access Register 0x95C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED88 Upper byte Masked Access Register 0x960 32 read-write n 0x0 0xFFFFFFFF UB_MASKED89 Upper byte Masked Access Register 0x964 32 read-write n 0x0 0xFFFFFFFF UB_MASKED9 Upper byte Masked Access Register 0x824 32 read-write n 0x0 0xFFFFFFFF UB_MASKED90 Upper byte Masked Access Register 0x968 32 read-write n 0x0 0xFFFFFFFF UB_MASKED91 Upper byte Masked Access Register 0x96C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED92 Upper byte Masked Access Register 0x970 32 read-write n 0x0 0xFFFFFFFF UB_MASKED93 Upper byte Masked Access Register 0x974 32 read-write n 0x0 0xFFFFFFFF UB_MASKED94 Upper byte Masked Access Register 0x978 32 read-write n 0x0 0xFFFFFFFF UB_MASKED95 Upper byte Masked Access Register 0x97C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED96 Upper byte Masked Access Register 0x980 32 read-write n 0x0 0xFFFFFFFF UB_MASKED97 Upper byte Masked Access Register 0x984 32 read-write n 0x0 0xFFFFFFFF UB_MASKED98 Upper byte Masked Access Register 0x988 32 read-write n 0x0 0xFFFFFFFF UB_MASKED99 Upper byte Masked Access Register 0x98C 32 read-write n 0x0 0xFFFFFFFF UB_MASKED[%s] Upper byte Masked Access Register 0x1000 32 read-write n 0x0 0xFFFFFFFF I2CM I2C Master I2C 0x40003000 0x0 0x100 registers n I2C 17 I2CBSEL I2C Bus Select 0x20 32 read-write n 0x0 0x1 I2CBSEL I2C Bus select 0 1 read-write 0 I2C_SCL connect to P0_04 and I2C_SCL connect to P0_05. 0 1 I2C_SCL connect to P0_10 and I2C_SCL connect to P0_11. 1 I2CMBUF I2C Master transmitted data Buffer 0x8 32 read-write n 0x0 0xFF D I2C Master write SEND data or read RECEIVE data 0 8 read-write I2CMCR I2C Master Control Register 0x4 32 write-only n 0x0 0xFF ACK Master in Receive mode need set this bit. This bit must work with RUN bit. 3 4 write-only 0 Read data follow by NAK 0 1 Read data follow by ACK 1 HS Transmission speed switch to High-speed. 4 5 write-only 0 No effect 0 1 Send START follow by Slave Address and Switching to High-speed. 1 RSTB Reset Bit for I2C Master 7 8 write-only 0 No effect 0 1 Reset I2C controller 1 RUN This bit work with START, STOP, ACK and HS. 0 1 write-only 0 No effect 0 1 Run a transmission 1 SLRST Slave Reset 6 7 write-only 0 No effect 0 1 Reset slaves connected to I2C bus by generating 9 I2C_SCK clocks followed by STOP. This bit need with RUN to work. 1 START Send START follow by Slave Address and SEND or RECEIVE. This bit need with RUN and RS to work. 1 2 write-only 0 No effect 0 1 Send START follow by Slave Address and SEND or RECEIVE. 1 STOP Send STOP and return to Idle mode, and transmission speed switch to Standard. 2 3 write-only 0 No effect 0 1 Send STOP 1 I2CMINT I2C Master Interrupt 0x1C 32 read-write n 0x0 0x3 I2CMIE I2C Master interrupt enable 0 1 read-write 0 Disable 0 1 Enable 1 I2CMIF I2C MASTER MODULE interrupt flag 1 2 read-write 0 No effect 0 1 I2C Master Interrupt occured. Write 1 to clean this bit. 1 I2CMSA I2C Master Slave address 0x0 32 read-write n 0x0 0xFF RS Receive or Send in START condition. This bit work with START, RUN or HS, RUN. 0 1 read-write 0 Transmitter 0 1 Receiver 1 SA Slave Address 1 8 read-write I2CMSR I2C Master Slave Register I2CMCR 0x4 32 read-only n 0x0 0xFF ARB_LOST Due the last operation I2C Bus controller lost the arbitration 4 5 read-only 0 not arbitration lost 0 1 has arbitration lost 1 BUSY I2C Master is receiving, or transmitting data on the bus and other bits of I2CMSR are no valid. 0 1 read-only 0 I2C Master controller not busy 0 1 I2C Master controller is busy 1 BUS_BUSY This bit is set by START conditions and reset by STOP conditions 6 7 read-only 0 Bus not busy 0 1 Bus is busy 1 DATA_ACK The acknowledged of DATA 3 4 read-only 0 DATA with NAK 0 1 DATA with ACK 1 ERROR Due the last operation an error occurred, that include slave address wasn't acknowledged, transmitted data wasn't acknowledged, or I2C Bus controller lost the arbitration. 1 2 read-only 0 Normal 0 1 Some error occurred 1 IDLE I2C Bus controller is in the idle state 5 6 read-only 0 I2C Bus controller is not in idle state 0 1 I2C Bus controller is in idle state 1 I2CMTP I2C Master Timer Period 0xC 32 read-write n 0x0 0x7F MTP I2C master timer period register. The range of MTP[6:0] is 1~63 0 7 read-write SCL_HP I2C_SCL High Period 0x14 32 read-write n 0x0 0xF SCL_HP I2C master SCL high time period register. The range of SCL_HP[3:0] is 2~15. 0 4 read-write SCL_LP I2C_SCL Low Period 0x10 32 read-write n 0x0 0xF SCL_LP I2C master SCL low time period register. The range of SCL_LP[3:0] is 1~14. 0 4 read-write SDA_SETUP I2C_DAT Setup Period 0x18 32 read-write n 0x0 0xF SDA_SETUP I2C Master SDA setup time register. The range of SDA_SETUP[3:0] is 2~15. 0 4 read-write I2CS I2C Slave I2C 0x40003800 0x0 0x100 registers n I2C 17 I2CSBUF I2C Slave Transmitted data Buffer 0x8 32 read-write n 0x0 0xFF D I2C Slave read data from D[7:0] when RREQ occurred, and write data to D[7:0] when TREQ occurred. 0 8 read-write I2CSCR I2C Slave Control Register 0x4 32 write-only n 0x0 0xFF DA I2C module Device Active 6 7 write-only 0 I2C Slave device inactive 0 1 I2C Slave device active 1 RECFINCLR RECFIN clear 3 4 write-only 0 No effect 0 1 Clear RECFIN flag 1 RSTB I2C Slave controller reset 7 8 write-only 0 No effect 0 1 Reset I2C Slave controller 1 SENDFINCLR Clear SENDFIN flag 2 3 write-only 0 No effect 0 1 Clear SENDFIN flag 1 I2CSINT I2C Slave Interrupt register 0x10 32 read-write n 0x0 0x3 I2CSIE I2C Slave device interrupt enable 0 1 read-write 0 Disable 0 1 Enable 1 I2CSIF I2C Slave device interrupt flag 1 2 read-write 0 No effect 0 1 I2C Slave device interrupt occurred. Write 1 to clear this bit 1 I2CSOA I2C Slave Own Address 0x0 32 read-write n 0x0 0x7F ADDR Slave device 7bits own address 0 7 read-write I2CSOAUP I2C Salve Own Address UP 0xC 32 read-write n 0x0 0xF ADDR9_7 The higher 3 bits for I2C Slave device 10bits own address. 0 3 read-write TEN_ADDR_EN Ten bits address enable 3 4 read-write 0 I2C Slave device using 7bits address 0 1 I2C Slave device using 10bits address 1 I2CSSR I2C Slave Status Register I2CSCR 0x4 32 read-only n 0x0 0xFF BUSACTIVE BUS ACTIVE 4 5 read-only 0 Bus no any transmission 0 1 Bus has any transmission 1 DA I2C slave Device Active 6 7 read-only 0 I2C slave device inactive 0 1 I2C slave device active 1 RECFIN Receive Finish 3 4 read-only 0 No effect 0 1 I2C Slave device receive finish. User need write 1 to RECFINCLR to clear this bit. 1 RREQ Receive Request 0 1 read-only 0 No receive request 0 1 Receive request occurred. User need read data from I2CSBUF to clear this bit. 1 SENDFIN Send Finish 2 3 read-only 0 No effect 0 1 I2C Slave device send finish. User need write 1 to SENDFINCLR to clear this bit. 1 TREQ Transmit Request 1 2 read-only 0 No transmit request 0 1 I2C Slave device is addressed as transmitter and requires data from host. User need write data to I2CBUF to clear this bit. 1 TIMER0 Timer TIMER 0x40000000 0x0 0x100 registers n TIMER0 8 TMR0_CTRL Timer 0 Control Register 0x0 32 read-write n 0x0 0xF CTRL0 Enable decrement control 0 1 read-write 0 Disable (Timer stop decrement) 0 1 Enable (Timer start decrement) 1 CTRL1 Select external input as enable 1 2 read-write 0 Disable 0 1 Enable (Timer stop when EXTIN=0) 1 CTRL2 Select external input as clock 2 3 read-write 0 Disable 0 1 Enable (Timer decrement when EXTIN rising edge) 1 CTRL3 Timer interrupt enable 3 4 read-write 0 Disable 0 1 Enable 1 TMR0_INT Timer 0 Interrupt Status Register 0xC 32 read-write n 0x0 0x1 INTSTATUS interrupt status (TIMERINT status) 0 1 read-write 0 Interrupt not occur 0 1 Interrupt occur, write 1 to clear INTSTATUS 1 TMR0_RELOAD Timer 0 Reload Register 0x8 32 read-write n 0x0 0xFFFFFFFF TMR0_VALUE Timer 0 Current Value Register 0x4 32 read-write n 0x0 0xFFFFFFFF TIMER1 Timer TIMER 0x40001000 0x0 0x100 registers n TIMER1 9 TMR1_CTRL Timer 1 Control Register 0x0 32 read-write n 0x0 0xF CTRL0 Enable decrement control 0 1 read-write 0 Disable (Timer stop decrement) 0 1 Enable (Timer start decrement) 1 CTRL1 Select external input as enable 1 2 read-write 0 Disable 0 1 Enable (Timer stop when EXTIN=0) 1 CTRL2 Select external input as clock 2 3 read-write 0 Disable 0 1 Enable (Timer decrement when EXTIN rising edge) 1 CTRL3 Timer interrupt enable 3 4 read-write 0 Disable 0 1 Enable 1 TMR1_INT Timer 1 Interrupt Status Register 0xC 32 read-write n 0x0 0x1 INTSTATUS interrupt status (TIMERINT status) 0 1 read-write 0 Interrupt not occur 0 1 Interrupt occur, write 1 to clear INTSTATUS 1 TMR1_RELOAD Timer 1 Reload Register 0x8 32 read-write n 0x0 0xFFFFFFFF TMR1_VALUE Timer 1 Current Value Register 0x4 32 read-write n 0x0 0xFFFFFFFF UART0 Timer UART 0x40004000 0x0 0x100 registers n UART0 1 UART_BAUDDIV UART Baud rate divider register 0x10 32 read-write n 0x0 0xFFFFF UART_CTRL UART Control Register 0x8 32 read-write n 0x0 0x3F CTRL0 TX enable 0 1 read-write 0 Disable UART TX 0 1 Enable UART TX 1 CTRL1 RX enable 1 2 read-write 0 Disable UART RX 0 1 Enable UART RX 1 CTRL2 TX interrupt enable 2 3 read-write 0 Disable UART TX interrupt 0 1 Enable UART TX interrupt 1 CTRL3 RX buffer overrun 3 4 read-write 0 Disable UART RX interrupt 0 1 Enable UART RX interrupt 1 CTRL4 TX overrun interrupt enable 4 5 read-write 0 Disable UART TX overrun interrupt 0 1 Enable UART TX overrun interrupt 1 CTRL5 RX overrun interrupt enable 5 6 read-write 0 Disable UART RX overrun interrupt 0 1 Enable UART RX overrun interrupt 1 UART_DATA UART Data Register 0x0 32 read-write n 0x0 0xFF UART_INT UART interrupt state and clear Register 0xC 32 read-write n 0x0 0xF INT0 TX interrupt 0 1 read-write 0 TX interrupt does not occur 0 1 TX interrupt has occurred. Write 1 to clear this bit 1 INT1 RX interrupt 1 2 read-write 0 RX interrupt does not occur 0 1 RX interrupt has occurred. Write 1 to clear this bit 1 INT2 TX overrun interrupt 2 3 read-write 0 TX overrun interrupt does not occur 0 1 TX overrun interrupt has occurred. Write 1 to clear this bit 1 INT3 RX buffer overrun 3 4 read-write 0 RX overrun interrupt does not occur 0 1 RX overrun interrupt has occurred. Write 1 to clear this bit 1 UART_STATE UART Status Register 0x4 32 read-write n 0x0 0xF STATE0 TX buffer full 0 1 read-only 0 TX buffer not full 0 1 TX buffer full 1 STATE1 RX buffer full 1 2 read-only 0 RX buffer not full 0 1 RX buffer full 1 STATE2 TX buffer overrun 2 3 read-write 0 TX Buffer does not overrun 0 1 TX Buffer has overrun. Write 1 to clean this bit 1 STATE3 RX buffer overrun 3 4 read-write 0 RX Buffer does not overrun 0 1 RX Buffer has overrun. Write 1 to clean this bit 1 UART1 Timer UART 0x40005000 0x0 0x100 registers n UART1 13 UART_BAUDDIV UART Baud rate divider register 0x10 32 read-write n 0x0 0xFFFFF UART_CTRL UART Control Register 0x8 32 read-write n 0x0 0x3F CTRL0 TX enable 0 1 read-write 0 Disable UART TX 0 1 Enable UART TX 1 CTRL1 RX enable 1 2 read-write 0 Disable UART RX 0 1 Enable UART RX 1 CTRL2 TX interrupt enable 2 3 read-write 0 Disable UART TX interrupt 0 1 Enable UART TX interrupt 1 CTRL3 RX buffer overrun 3 4 read-write 0 Disable UART RX interrupt 0 1 Enable UART RX interrupt 1 CTRL4 TX overrun interrupt enable 4 5 read-write 0 Disable UART TX overrun interrupt 0 1 Enable UART TX overrun interrupt 1 CTRL5 RX overrun interrupt enable 5 6 read-write 0 Disable UART RX overrun interrupt 0 1 Enable UART RX overrun interrupt 1 UART_DATA UART Data Register 0x0 32 read-write n 0x0 0xFF UART_INT UART interrupt state and clear Register 0xC 32 read-write n 0x0 0xF INT0 TX interrupt 0 1 read-write 0 TX interrupt does not occur 0 1 TX interrupt has occurred. Write 1 to clear this bit 1 INT1 RX interrupt 1 2 read-write 0 RX interrupt does not occur 0 1 RX interrupt has occurred. Write 1 to clear this bit 1 INT2 TX overrun interrupt 2 3 read-write 0 TX overrun interrupt does not occur 0 1 TX overrun interrupt has occurred. Write 1 to clear this bit 1 INT3 RX buffer overrun 3 4 read-write 0 RX overrun interrupt does not occur 0 1 RX overrun interrupt has occurred. Write 1 to clear this bit 1 UART_STATE UART Status Register 0x4 32 read-write n 0x0 0xF STATE0 TX buffer full 0 1 read-only 0 TX buffer not full 0 1 TX buffer full 1 STATE1 RX buffer full 1 2 read-only 0 RX buffer not full 0 1 RX buffer full 1 STATE2 TX buffer overrun 2 3 read-write 0 TX Buffer does not overrun 0 1 TX Buffer has overrun. Write 1 to clean this bit 1 STATE3 RX buffer overrun 3 4 read-write 0 RX Buffer does not overrun 0 1 RX Buffer has overrun. Write 1 to clean this bit 1 WATCHDOG Watchdog WATCHDOG 0x40008000 0x0 0x1000 registers n ITCR Watchdog Integration Test Control Register 0xF00 32 read-write n 0x0 0xFFFFFFFF ITOP Watchdog Integration Test Output Set Register 0xF04 32 write-only n 0x0 0xFFFFFFFF WDOGCTRL Watchdog Control Register 0x8 32 read-write n 0x0 0x3 INTEN Watchdog counter and interrupt enable 0 1 read-write 0 Disable counter and interrupt 0 1 Enable counter and interrupt 1 RESTEN Enable watchdog reset 1 2 read-write 0 Watchdog reset disable 0 1 Watchdog reset enable 1 WDOGINTCLR Watchdog Interrupt Clean Register 0xC 32 write-only n 0x0 0xFFFFFFFF INTCLR A write of any value to clear the watchdog interrupt, and reloads the counter from the value in LOAD. 0 32 read-write WDOGLOAD Watchdog Load Register 0x0 32 read-write n 0x0 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 32 read-write n 0x0 0xFFFFFFFF LOCK Enable register writes Enable write access to all other registers by writing 0x1ACCE551. Disable write access by writing any other value. 0 32 read-write WDOGMIS Watchdog Enabled Interrupt Status Register 0x14 32 read-only n 0x0 0x1 MASKINTSTAT Watchdog Interrupt Enabled interrupt status from the counter 0 1 read-only 0 Watchdog interrupt not occur 0 1 Watchdog Interrupt occur 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 32 read-only n 0x0 0x1 RAWINTSTAT Raw Watchdog Interrupt Raw interrupt status from the counter 0 1 read-only 0 Raw watchdog interrupt not occur 0 1 Raw watchdog Interrupt occur 1 WDOGVALUE Watchdog Value Register 0x4 32 read-only n 0x0 0xFFFFFFFF